[RFC PATCH 11.0 1/2]

[2358543632]

TCGOutOpBinary passes (output, value, count), but MIPS variable shift
instructions encode (rd, rt, rs), where rt is the value and rs is the
count. tcg_out_opc_reg() takes its register fields in (rd, rs, rt)
order, so passing (a0, a1, a2) encodes the value as the count and the
count as the value.


Swap a1 and a2 at the four variable shift emitters. This covers the I32
and I64 forms of SHL, SHR, SAR, and ROTR.


A freestanding AArch64 test forces each operation into a separate
translation block and records one failure bit per form. With QEMU 11.0.3
in a pre-R6 MIPS64EL execution environment:


  unpatched: exit status 0xff
  patched:   exit status 0x00


For example, the DSRAV host instruction changes from:


  dsrav s0,s0,s1


to:


  dsrav s0,s1,s0


where s1 contains the value and s0 contains the count at that point.


Fixes: 03568c0d5395 ("tcg: Convert rotl, rotr to TCGOutOpBinary")
Fixes: b5aafbaa8346 ("tcg: Convert sar to TCGOutOpBinary")
Fixes: 27d21ee7c791 ("tcg: Convert shl to TCGOutOpBinary")
Fixes: edd6ba8a6bc8 ("tcg: Convert shr to TCGOutOpBinary")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4103
Signed-off-by: Quintin Kong <2358543...@qq.com&gt;
---
&nbsp;tcg/mips64/tcg-target.c.inc | 8 ++++----
&nbsp;1 file changed, 4 insertions(+), 4 deletions(-)


diff --git a/tcg/mips64/tcg-target.c.inc b/tcg/mips64/tcg-target.c.inc
index 60c703a09..2b34f3716 100644
--- a/tcg/mips64/tcg-target.c.inc
+++ b/tcg/mips64/tcg-target.c.inc
@@ -1836,7 +1836,7 @@ static void tgen_rotr(TCGContext *s, TCGType type,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 
TCGReg a0, TCGReg a1, TCGReg a2)
&nbsp;{
&nbsp; &nbsp; &nbsp;MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : 
OPC_DROTRV;
- &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a1, a2);
+ &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a2, a1);
&nbsp;}
&nbsp;
&nbsp;static void tgen_rotri(TCGContext *s, TCGType type,
@@ -1860,7 +1860,7 @@ static void tgen_sar(TCGContext *s, TCGType type,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 
TCGReg a0, TCGReg a1, TCGReg a2)
&nbsp;{
&nbsp; &nbsp; &nbsp;MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV;
- &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a1, a2);
+ &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a2, a1);
&nbsp;}
&nbsp;
&nbsp;static void tgen_sari(TCGContext *s, TCGType type,
@@ -1883,7 +1883,7 @@ static void tgen_shl(TCGContext *s, TCGType type,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 
TCGReg a0, TCGReg a1, TCGReg a2)
&nbsp;{
&nbsp; &nbsp; &nbsp;MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV;
- &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a1, a2);
+ &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a2, a1);
&nbsp;}
&nbsp;
&nbsp;static void tgen_shli(TCGContext *s, TCGType type,
@@ -1906,7 +1906,7 @@ static void tgen_shr(TCGContext *s, TCGType type,
&nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; &nbsp; 
TCGReg a0, TCGReg a1, TCGReg a2)
&nbsp;{
&nbsp; &nbsp; &nbsp;MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV;
- &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a1, a2);
+ &nbsp; &nbsp;tcg_out_opc_reg(s, insn, a0, a2, a1);
&nbsp;}
&nbsp;
&nbsp;static void tgen_shri(TCGContext *s, TCGType type,
--
2.43.0