On Sun, 2026-08-09 at 15:35 -0700, Richard Henderson wrote: > These entire base opcodes are RV64. Reject them all at once > rather than one at a time. > > Signed-off-by: Richard Henderson <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > disas/riscv.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/disas/riscv.c b/disas/riscv.c > index c4b8ee7d07..f51d45674e 100644 > --- a/disas/riscv.c > +++ b/disas/riscv.c > @@ -3311,6 +3311,10 @@ static const rv_opcode_data > *decode_inst_opcode(rv_decode *dec, rv_isa isa) > } > break; > case 6: > + /* OP-IMM-32 */ > + if (isa == rv32) { > + break; > + } > switch ((inst >> 12) & 0b111) { > case 0: op = rv_op_addiw; break; > case 1: > @@ -3557,6 +3561,10 @@ static const rv_opcode_data > *decode_inst_opcode(rv_decode *dec, rv_isa isa) > break; > case 13: op = rv_op_lui; break; > case 14: > + /* OP-32 */ > + if (isa == rv32) { > + break; > + } > switch (((inst >> 22) & 0b1111111000) | > ((inst >> 12) & 0b0000000111)) { > case 0: op = rv_op_addw; break;
