On Tue, 2026-08-11 at 09:14 +0800, wangyang wrote: > Zfinx explicitly excludes the FMV transfer instructions, but > trans_fmv_x_w/trans_fmv_w_x used REQUIRE_ZFINX_OR_F so a Zfinx-only > CPU accepted them. Require RVF instead so the transfers trap with > an illegal instruction when only Zfinx is present. > > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4108 > Signed-off-by: wangyang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/tcg/insn_trans/trans_rvf.c.inc > b/target/riscv/tcg/insn_trans/trans_rvf.c.inc > index e935523c93c..305f545b494 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvf.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvf.c.inc > @@ -428,7 +428,8 @@ static bool trans_fmv_x_w(DisasContext *ctx, > arg_fmv_x_w *a) > { > /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! > */ > REQUIRE_FPU; > - REQUIRE_ZFINX_OR_F(ctx); > + /* Zfinx explicitly excludes the FMV transfer instructions. */ > + REQUIRE_EXT(ctx, RVF); > > TCGv dest = dest_gpr(ctx, a->rd); > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > @@ -531,7 +532,8 @@ static bool trans_fmv_w_x(DisasContext *ctx, > arg_fmv_w_x *a) > { > /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! > */ > REQUIRE_FPU; > - REQUIRE_ZFINX_OR_F(ctx); > + /* Zfinx explicitly excludes the FMV transfer instructions. */ > + REQUIRE_EXT(ctx, RVF); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv src = get_gpr(ctx, a->rs1, EXT_ZERO);
