On Tue, 2026-08-11 at 09:14 +0800, wangyang wrote: > fcvt.d.h and fcvt.h.d access a 64-bit double held in a register > pair, so under Zdinx/Zhinxmin the odd-rd (fcvt.d.h) and odd-rs1 > (fcvt.h.d) encodings are reserved. Add the missing REQUIRE_EVEN > checks so those encodings raise an illegal-instruction exception > instead of retiring. > > Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4109 > Signed-off-by: wangyang <[email protected]>
Reviewed-by: Alistair Francis <[email protected]> Alistair > --- > 1 file changed, 2 insertions(+), 0 deletions(-) > > diff --git a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc > b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc > index f36b46c2118..6ee71506d62 100644 > --- a/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc > +++ b/target/riscv/tcg/insn_trans/trans_rvzfh.c.inc > @@ -413,6 +413,7 @@ static bool trans_fcvt_d_h(DisasContext *ctx, > arg_fcvt_d_h *a) > REQUIRE_FPU; > REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rd); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv_i64 src1 = get_fpr_hs(ctx, a->rs1); > @@ -447,6 +448,7 @@ static bool trans_fcvt_h_d(DisasContext *ctx, > arg_fcvt_h_d *a) > REQUIRE_FPU; > REQUIRE_ZFHMIN_OR_ZHINXMIN(ctx); > REQUIRE_ZDINX_OR_D(ctx); > + REQUIRE_EVEN(ctx, a->rs1); > > TCGv_i64 dest = dest_fpr(ctx, a->rd); > TCGv_i64 src1 = get_fpr_d(ctx, a->rs1);
