Pass the internal SEC SRAM region and its base address to the secure boot controller (via the 'sram' link and 'sram-base' property) so its ECDSA engine can read the public key, signature and digest that the guest firmware stages there before triggering a verify.
Signed-off-by: Jamin Lin <[email protected]> --- hw/arm/aspeed_ast10x0.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 93c81195b5..8e34870856 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -357,6 +357,10 @@ static bool aspeed_soc_ast10x0_realize(Aspeed10x0SoCState *a, Error **errp) } /* Secure Boot Controller */ + object_property_set_link(OBJECT(&s->sbc), "sram", OBJECT(&s->sram[1]), + &error_abort); + qdev_prop_set_uint64(DEVICE(&s->sbc), "sram-base", + sc->memmap[ASPEED_DEV_SRAM1]); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sbc), errp)) { return false; } -- 2.53.0
