The SBC controller register space is 0x1000. Increase ASPEED_SBC_NR_REGS accordingly to cover the full register space.
Bump the VMState version to 2. Signed-off-by: Jamin Lin <[email protected]> --- hw/misc/aspeed_sbc.c | 4 ++-- include/hw/misc/aspeed_sbc.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index 724f4cb06c..951dde5126 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -464,8 +464,8 @@ static void aspeed_sbc_realize(DeviceState *dev, Error **errp) static const VMStateDescription vmstate_aspeed_sbc = { .name = TYPE_ASPEED_SBC, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, AspeedSBCState, ASPEED_SBC_NR_REGS), VMSTATE_END_OF_LIST(), diff --git a/include/hw/misc/aspeed_sbc.h b/include/hw/misc/aspeed_sbc.h index 9b04a10aed..e37c3a12dd 100644 --- a/include/hw/misc/aspeed_sbc.h +++ b/include/hw/misc/aspeed_sbc.h @@ -17,7 +17,7 @@ #define TYPE_ASPEED_AST10X0_SBC TYPE_ASPEED_SBC "-ast10x0" OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC) -#define ASPEED_SBC_NR_REGS (0x93c >> 2) +#define ASPEED_SBC_NR_REGS (0x1000 >> 2) #define QSR_AES BIT(27) #define QSR_RSA1024 (0x0 << 12) -- 2.53.0
