GPCYCLELO/GPCYCLEHI read as zero unless the cycle counter is enabled (SSR:CE), matching the hardware.
Signed-off-by: Brian Cain <[email protected]> --- target/hexagon/cpu.c | 7 +++++-- target/hexagon/op_helper.c | 9 ++------- 2 files changed, 7 insertions(+), 9 deletions(-) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 0bbefc2fb87..0a677840bcb 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -809,14 +809,17 @@ static void hexagon_cpu_class_init(ObjectClass *c, const void *data) #ifndef CONFIG_USER_ONLY uint32_t hexagon_greg_read(CPUHexagonState *env, uint32_t reg) { + uint32_t ssr = env->t_sreg[HEX_SREG_SSR]; + int ssr_ce = GET_SSR_FIELD(SSR_CE, ssr); + if (reg <= HEX_GREG_G3) { return env->greg[reg]; } switch (reg) { case HEX_GREG_GPCYCLELO: - return hexagon_get_sys_pcycle_count_low(env); + return ssr_ce ? hexagon_get_sys_pcycle_count_low(env) : 0; case HEX_GREG_GPCYCLEHI: - return hexagon_get_sys_pcycle_count_high(env); + return ssr_ce ? hexagon_get_sys_pcycle_count_high(env) : 0; default: qemu_log_mask(LOG_UNIMP, "reading greg %" PRId32 " not yet supported.\n", reg); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 23894ff3d28..2cea1927263 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -1912,13 +1912,8 @@ uint64_t HELPER(greg_read_pair)(CPUHexagonState *env, uint32_t reg) return (uint64_t)(env->greg[reg]) | (((uint64_t)(env->greg[reg + 1])) << 32); } - switch (reg) { - case HEX_GREG_GPCYCLELO: - return hexagon_get_sys_pcycle_count(env); - default: - return (uint64_t)hexagon_greg_read(env, reg) | - ((uint64_t)(hexagon_greg_read(env, reg + 1)) << 32); - } + return (uint64_t)hexagon_greg_read(env, reg) | + ((uint64_t)(hexagon_greg_read(env, reg + 1)) << 32); } /* -- 2.34.1
