Changes to address some test cases:
- user/system mode exception consolidation
- Direct-to-Guest interrupt delivery
- interrupt mask writes, tlb probe exception
- l2vic edge-trigger clear on deassert
- map architectural timer regs to clock
Brian Cain (10):
target/hexagon: align exceptions for user/sysemu
tests/tcg/hexagon: check priv instructions raise SIGILL
target/hexagon: guard writes to unimplemented guest registers
target/hexagon: take BQL when reading the system pcycle count
target/hexagon: gate GPCYCLE guest register reads on SSR:CE
target/hexagon: read UTIMERLO/UTIMERHI from the global timer
target/hexagon: raise imprecise exception on multi-TLB match
target/hexagon: implement direct-to-guest interrupt delivery
target/hexagon: fix iassign{r,w} to cover all threads
tests/functional/hexagon: update to v0.2.12,
+test_{interrupts,sys_regs}
Sid Manning (1):
hw/intc: clear pending bit on l2vic de-assertion
include/hw/hexagon/hexagon_tlb.h | 3 +-
target/hexagon/cpu.h | 1 +
target/hexagon/helper.h | 4 +
target/hexagon/translate.h | 9 ++-
target/hexagon/reg_fields_def.h.inc | 7 ++
hw/hexagon/hexagon_tlb.c | 5 +-
hw/intc/hex-l2vic.c | 2 +
linux-user/hexagon/cpu_loop.c | 30 +++----
target/hexagon/cpu.c | 15 +++-
target/hexagon/cpu_helper.c | 12 ++-
target/hexagon/genptr.c | 29 +++++++
target/hexagon/hex_interrupts.c | 87 +++++++++++++++++++--
target/hexagon/hex_mmu.c | 5 +-
target/hexagon/hexswi.c | 37 ++++++++-
target/hexagon/machine.c | 5 +-
target/hexagon/op_helper.c | 72 ++++++++---------
target/hexagon/translate.c | 56 ++++++++-----
tests/tcg/hexagon/privileged-insn.c | 79 +++++++++++++++++++
tests/tcg/hexagon/reg_mut.c | 11 ++-
target/hexagon/hex_common.py | 18 ++++-
tests/functional/hexagon/test_arch_tests.py | 12 ++-
tests/tcg/hexagon/Makefile.target | 1 +
22 files changed, 392 insertions(+), 108 deletions(-)
create mode 100644 tests/tcg/hexagon/privileged-insn.c
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2.34.1
