When the guest writes to IRS_IST_BASER we effectively cache the value of the VALID bit in the GICv5ISTConfig valid field entry. In a few places we check whether the IST is valid by doing a bit extract on the register value; switch those to look at cfg->structure instead.
Signed-off-by: Peter Maydell <[email protected]> --- hw/intc/arm_gicv5.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c index 7480c12413b..8ffb2a49020 100644 --- a/hw/intc/arm_gicv5.c +++ b/hw/intc/arm_gicv5.c @@ -1223,8 +1223,7 @@ static void irs_map_l2_istr_write(GICv5 *s, GICv5Domain domain, uint64_t value) uint64_t l1_iste; MemTxResult res; - if (!FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID) || - !cfg->structure) { + if (!cfg->valid || !cfg->structure) { /* WI if no IST set up or it is not 2-level */ return; } @@ -1294,7 +1293,7 @@ static void irs_ist_baser_write(GICv5 *s, GICv5Domain domain, uint64_t value) { GICv5Common *cs = ARM_GICV5_COMMON(s); - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { /* If VALID is set, ADDR is RO and we can only update VALID */ bool valid = FIELD_EX64(value, IRS_IST_BASER, VALID); if (valid) { @@ -1604,7 +1603,7 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset, deposit64(cs->irs_ist_baser[domain], 32, 32, data)); return true; case A_IRS_IST_CFGR: - if (FIELD_EX64(cs->irs_ist_baser[domain], IRS_IST_BASER, VALID)) { + if (s->phys_lpi_config[domain].valid) { qemu_log_mask(LOG_GUEST_ERROR, "guest tried to write IRS_IST_CFGR for %s config frame " "while IST_BASER.VALID set\n", domain_name[domain]); -- 2.43.0
