This patchset is a compilation of minor fixes and cleanups to the GICv5 code that I found in the course of implementing virtualization support:
* Various in-memory data structures are defined to be aligned to their size, even if the guest provides a base address that is less aligned * We had some extra blank lines that didn't match the style in the rest of the file * We were unnecessarily extracting a bit from a raw register value when we already had it cached as a boolean in a struct * We weren't tidying up our allocated memory on finalize * We can re-use arm_cpu_set_irq() rather than implementing the set/clear IRQ/FIQ/NMI locally. (This doesn't matter much for these, but VIRQ/VFIQ/VINMI have more complex logic in arm_cpu_set_irq() that we don't want to have to duplicate.) thanks -- PMM Peter Maydell (6): hw/intc/arm_gicv5: Ignore low bits in IRS_IST_BASER.ADDR hw/intc/arm_gicv5: Ignore low bits in L1_ISTE.L2_ADDR hw/intc/arm_gicv5: Regularize spacing in config_readl() switch hw/intc/arm_gicv5: Use cached IRS_IST_BASER.VALID state hw/intc/arm_gicv5: Free memory in finalize target/arm: GICv5 cpuif: Use arm_cpu_set_irq() to set IRQ/FIQ status hw/intc/arm_gicv5.c | 67 ++++++++++++++++++++++++++---------- hw/intc/arm_gicv5_common.c | 3 ++ include/hw/intc/arm_gicv5.h | 1 + target/arm/cpu.c | 14 ++++++-- target/arm/internals.h | 14 ++++++++ target/arm/tcg/gicv5-cpuif.c | 35 +++---------------- 6 files changed, 81 insertions(+), 53 deletions(-) -- 2.43.0
