From: Richard Henderson <[email protected]> th.lbib should format the same as th.lbia, and the other increment insns, with the address register in parenthesis.
Cc: [email protected] Fixes: 318df7238b9 ("disas/riscv: Add support for XThead* instructions") Reviewed-by: Alistair Francis <[email protected]> Signed-off-by: Richard Henderson <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit ecbd3a031f12669da98cdf929cbc7dbb88d3450f) (Mjt: fix-up across v11.1.0-496-g7de6afd53186 "disas/riscv: Drop explicit zero of rv_opcode_data fields") Signed-off-by: Michael Tokarev <[email protected]> diff --git a/disas/riscv-xthead.c b/disas/riscv-xthead.c index 2f2ddb8dd9a..1df92313669 100644 --- a/disas/riscv-xthead.c +++ b/disas/riscv-xthead.c @@ -189,7 +189,7 @@ const rv_opcode_data xthead_opcode_data[] = { { "th.mulsh", rv_codec_r, rv_fmt_rd_rs1_rs2, NULL, 0, 0, 0 }, /* XTheadMemIdx */ { "th.lbia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, - { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml, NULL, 0, 0, 0 }, + { "th.lbib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, { "th.lbuia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, { "th.lbuib", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, { "th.lhia", rv_codec_r2_imm2_imm5, rv_fmt_rd_rs1_immh_imml_addr, NULL, 0, 0, 0 }, -- 2.47.3
