Initial commit of N-Trace support patch series based on "RISC-V n-trace (Nexus-based Trace) Specification" Version 1.0. With Trace control devices based on "RISC-V Trace Control Interface Specification" Version 1.0.
Selecting trace message format rely on trTeFormat bit of trTeControl trace encoder register. We will mirror trTeFormat value in trace encoder in `ntrace` field to simplify checking of current format in trace encoder logic. This commit only mirrors register value in field, logic based on this field value is added in next commit. Signed-off-by: Konstantin Semichastnov <[email protected]> --- hw/riscv/trace-encoder.c | 22 +++++++++++++++++++++- hw/riscv/trace-encoder.h | 2 ++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/hw/riscv/trace-encoder.c b/hw/riscv/trace-encoder.c index 55acb1f2ae..53345a478c 100644 --- a/hw/riscv/trace-encoder.c +++ b/hw/riscv/trace-encoder.c @@ -84,6 +84,9 @@ REG32(TR_TE_CONTROL, 0x0) #define R_TR_TE_CONTROL_RESET R_TR_TE_CONTROL_EMPTY_MASK #define R_TR_TE_CONTROL_RO_BITS R_TR_TE_CONTROL_EMPTY_MASK +#define TR_TE_CONTROL_FORMAT_ETRACE 0 +#define TR_TE_CONTROL_FORMAT_NTRACE 1 + /* * trTeImpl register fields */ @@ -153,7 +156,6 @@ static uint64_t trencoder_te_ctrl_set_hardwire_vals(uint64_t input) input = FIELD_DP32(input, TR_TE_CONTROL, CONTEXT, 0); input = FIELD_DP32(input, TR_TE_CONTROL, INST_STALL_ENA, 0); input = FIELD_DP32(input, TR_TE_CONTROL, INHIBIT_SRC, 1); - input = FIELD_DP32(input, TR_TE_CONTROL, FORMAT, 0); /* SYNC_MODE and SYNC_MAX will be revisited */ input = FIELD_DP32(input, TR_TE_CONTROL, INST_SYNC_MODE, 0); @@ -168,6 +170,7 @@ static uint64_t trencoder_te_ctrl_prew(RegisterInfo *reg, uint64_t val) uint32_t trTeActive = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ACTIVE); uint32_t trTeInstTracing = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, INST_TRACING); + uint32_t trTeFormat = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, FORMAT); uint32_t temp; val = trencoder_te_ctrl_set_hardwire_vals(val); @@ -205,6 +208,19 @@ static uint64_t trencoder_te_ctrl_prew(RegisterInfo *reg, uint64_t val) val = FIELD_DP32(val, TR_TE_CONTROL, INST_TRACING, 0); } + temp = FIELD_EX32(val, TR_TE_CONTROL, FORMAT); + if (te->trace_running) { + /* Do not allow to change tracing format while tracing is enabled. */ + val = FIELD_DP32(val, TR_TE_CONTROL, FORMAT, trTeFormat); + } else if (temp != TR_TE_CONTROL_FORMAT_ETRACE && + temp != TR_TE_CONTROL_FORMAT_NTRACE) { + /* + * Do not change format, if requested format is not supported + * (only E-Trace and N-Trace formats are supported for now) + */ + val = FIELD_DP32(val, TR_TE_CONTROL, FORMAT, trTeFormat); + } + return val; } @@ -215,6 +231,7 @@ static void trencoder_te_ctrl_postw(RegisterInfo *reg, uint64_t val) uint32_t trTeEnable = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, ENABLE); uint32_t trTeInstTracing = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, INST_TRACING); + uint32_t trTeFormat = ARRAY_FIELD_EX32(te->regs, TR_TE_CONTROL, FORMAT); RISCVCPU *cpu = te->cpu; CPURISCVState *env = &cpu->env; @@ -233,6 +250,8 @@ static void trencoder_te_ctrl_postw(RegisterInfo *reg, uint64_t val) te->enabled = trTeEnable ? true : false; + te->ntrace = (trTeFormat == TR_TE_CONTROL_FORMAT_NTRACE); + if (!te->trace_running && trTeInstTracing) { /* Starting trace. Ask the CPU for the first trace insn */ te->trace_next_insn = true; @@ -314,6 +333,7 @@ static void trencoder_reset(DeviceState *dev) te->enabled = false; te->trace_running = false; te->trace_next_insn = false; + te->ntrace = false; env->trace_running = false; te->branch_map = 0; diff --git a/hw/riscv/trace-encoder.h b/hw/riscv/trace-encoder.h index 48cf8366ee..fed0ef9a48 100644 --- a/hw/riscv/trace-encoder.h +++ b/hw/riscv/trace-encoder.h @@ -44,6 +44,8 @@ struct TraceEncoder { bool enabled; bool trace_running; bool trace_next_insn; + + bool ntrace; }; #define TYPE_TRACE_ENCODER "trace-encoder" -- 2.43.0
