From: Dongjoo Seo <[email protected]> Implement the Streamlined Virtual Channel (SVC) extended capability for PCIe ports (Root, Upstream, and Downstream). This capability is mandatory for enabling Unordered IO (UIO) traffic as per PCIe 6.4 specification [1].
UIO functionality depends on two key prerequisites: 1. SVC 2. 256-byte Flit mode support This patch adds the following experimental properties to PCIe ports: - x-svc: Enable SVC in the port. - x-256b-flit: Enable 256B flit mode in the port. This change lays the groundwork for UIO emulation in QEMU. [1]: PCIe 6.4 Specification, Table 2-46 (Streamlined Virtual Channel). Signed-off-by: Dongjoo Seo <[email protected]> Signed-off-by: Shrihari E S <[email protected]> --- hw/pci-bridge/pcie_root_port.c | 1 + hw/pci-bridge/xio3130_downstream.c | 2 ++ hw/pci-bridge/xio3130_upstream.c | 7 +++++++ include/hw/pci/pcie_port.h | 3 +++ 4 files changed, 13 insertions(+) diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index eeee24e042..0ae7b10fbd 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -153,6 +153,7 @@ static const Property rp_props[] = { QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, true), + DEFINE_PROP_BOOL("x-svc", PCIEPort, svc, false), }; static void rp_instance_post_init(Object *obj) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 0c3fed3053..090a3fdfc9 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -137,6 +137,8 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), + DEFINE_PROP_BOOL("x-svc", PCIEPort, svc, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), }; static const VMStateDescription vmstate_xio3130_downstream = { diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 40057b749b..767b7d17f2 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -24,6 +24,7 @@ #include "hw/pci/msi.h" #include "hw/pci/pcie.h" #include "hw/pci/pcie_port.h" +#include "hw/core/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/module.h" @@ -123,6 +124,11 @@ static const VMStateDescription vmstate_xio3130_upstream = { } }; +static const Property xio3130_upstream_props[] = { + DEFINE_PROP_BOOL("x-svc", PCIEPort, svc, false), + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false), +}; + static void xio3130_upstream_class_init(ObjectClass *klass, const void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -138,6 +144,7 @@ static void xio3130_upstream_class_init(ObjectClass *klass, const void *data) dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; device_class_set_legacy_reset(dc, xio3130_upstream_reset); dc->vmsd = &vmstate_xio3130_upstream; + device_class_set_props(dc, xio3130_upstream_props); } static const TypeInfo xio3130_upstream_info = { diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 1bcc734649..0b3e0efb8c 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -37,6 +37,9 @@ struct PCIEPort { /* pci express switch port */ uint8_t port; + + /* Streamlined Virtual Channel (SVC) capability */ + bool svc; }; void pcie_port_init_reg(PCIDevice *d); -- 2.34.1
