Hi Shrihari,
On Wed, 26 Aug 2026 11:04:03 +0530, Shrihari E S wrote:
> +static const Property xio3130_upstream_props[] = {
> + DEFINE_PROP_BOOL("x-svc", PCIEPort, svc, false),
> + DEFINE_PROP_BOOL("x-256b-flit", PCIEPort, flitmode, false),
> +};
x-256b-flit is a no-op on x3130-upstream: nothing in
xio3130_upstream.c reads PCIEPort::flitmode. pcie_cap_fill_slot_lnk()
does run from pcie_cap_init(), but returns early -- an upstream port is
a PCIEPort, not a PCIESlot -- and pcie_cap_fill_link_ep_usp(), the path
cxl-upstream and cxl-type3 take, isn't called here. So with
x-256b-flit=on the Flags bit 15 and LNKSTA2 flit bits stay 0. I'd
either wire up pcie_cap_fill_link_ep_usp() the way cxl-upstream does,
from its reset handler, or drop x-256b-flit from this hunk.
x-svc has no reader until 7/10 either, so x-svc=on has no effect for
four commits. Same thing Jonathan asked for on v1: bring the state in
with the patch that uses it. Here that would fold 3 and 4 into 7.
Many thanks,
Junjie
