Integrate Streamlined Virtual Channel (SVC) capability initialization into the realize() functions of both PCIe and CXL ports. This change ensures that the 'uio_capable' flag is correctly populated in CXL ports during the initialization sequence.
'uio_capable' in CXL ports is responsible for enabling UIO capability in HDM decoder registers. Signed-off-by: Shrihari E S <[email protected]> Signed-off-by: Dongjoo Seo <[email protected]> --- hw/pci-bridge/cxl_downstream.c | 7 ++++++- hw/pci-bridge/cxl_root_port.c | 11 ++++++++++- hw/pci-bridge/cxl_upstream.c | 10 +++++++++- hw/pci-bridge/gen_pcie_root_port.c | 3 +++ hw/pci-bridge/pcie_root_port.c | 4 ++++ hw/pci-bridge/xio3130_downstream.c | 3 +++ hw/pci-bridge/xio3130_upstream.c | 3 +++ include/hw/pci/pcie_port.h | 1 + 8 files changed, 39 insertions(+), 3 deletions(-) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index 8f034991d8..de6d2f7306 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -33,8 +33,10 @@ typedef struct CXLDownstreamPort { #define CXL_DOWNSTREAM_PORT_MSI_NR_VECTOR 2 #define CXL_DOWNSTREAM_PORT_EXP_OFFSET 0x90 #define CXL_DOWNSTREAM_PORT_AER_OFFSET 0x100 -#define CXL_DOWNSTREAM_PORT_DVSEC_OFFSET \ +#define CXL_DOWNSTREAM_PORT_SVC_OFFSET \ (CXL_DOWNSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF) +#define CXL_DOWNSTREAM_PORT_DVSEC_OFFSET \ + (CXL_DOWNSTREAM_PORT_SVC_OFFSET + PCI_SVC_SIZEOF) static void latch_registers(CXLDownstreamPort *dsp) { @@ -229,6 +231,9 @@ static void cxl_dsp_realize(PCIDevice *d, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &dsp->bar); + if (p->svc) { + pcie_svc_cap_init(d, CXL_DOWNSTREAM_PORT_SVC_OFFSET, errp); + } return; diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 4be2b400f9..19dd75b79f 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -40,8 +40,10 @@ #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) -#define CXL_ROOT_PORT_DVSEC_OFFSET \ +#define GEN_PCIE_ROOT_PORT_SVC_OFFSET \ (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) +#define CXL_ROOT_PORT_DVSEC_OFFSET \ + (GEN_PCIE_ROOT_PORT_SVC_OFFSET + PCI_SVC_SIZEOF) typedef struct CXLRootPort { /*< private >*/ @@ -164,6 +166,7 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) { PCIDevice *pci_dev = PCI_DEVICE(dev); PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); + PCIEPort *p = PCIE_PORT(dev); CXLRootPort *crp = CXL_ROOT_PORT(dev); CXLComponentState *cxl_cstate = &crp->cxl_cstate; ComponentRegisters *cregs = &cxl_cstate->crb; @@ -212,6 +215,12 @@ static void cxl_rp_realize(DeviceState *dev, Error **errp) PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &crp->bar); + if (p->svc) { + rc = pcie_svc_cap_init(pci_dev, GEN_PCIE_ROOT_PORT_SVC_OFFSET, errp); + if (p->flitmode && rc >= 0) { + crp->uio_capable = true; + } + } } static void cxl_rp_reset_hold(Object *obj, ResetType type) diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index e8f2e57819..3ed6a89bf3 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -27,8 +27,10 @@ #define CXL_UPSTREAM_PORT_MSI_OFFSET 0x70 #define CXL_UPSTREAM_PORT_PCIE_CAP_OFFSET 0x90 #define CXL_UPSTREAM_PORT_AER_OFFSET 0x100 +#define CXL_UPSTREAM_PORT_SVC_OFFSET \ + (CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF) #define CXL_UPSTREAM_PORT_SN_OFFSET \ - (CXL_UPSTREAM_PORT_AER_OFFSET + PCI_ERR_SIZEOF) + (CXL_UPSTREAM_PORT_SVC_OFFSET + PCI_SVC_SIZEOF) #define CXL_UPSTREAM_PORT_DVSEC_OFFSET \ (CXL_UPSTREAM_PORT_SN_OFFSET + PCI_EXT_CAP_DSN_SIZEOF) @@ -411,6 +413,12 @@ static void cxl_usp_realize(PCIDevice *d, Error **errp) goto err_cap; } + if (p->svc) { + rc = pcie_svc_cap_init(d, CXL_UPSTREAM_PORT_SVC_OFFSET, errp); + if (p->flitmode && rc >= 0) { + usp->uio_capable = true; + } + } return; err_cap: diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index 2f7257d166..d4df4a7c16 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -26,6 +26,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(GenPCIERootPort, GEN_PCIE_ROOT_PORT) #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \ (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF) +#define GEN_PCIE_ROOT_PORT_SVC_OFFSET \ + (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF) #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR 1 #define GEN_PCIE_ROOT_DEFAULT_IO_RANGE 4096 @@ -166,6 +168,7 @@ static void gen_rp_dev_class_init(ObjectClass *klass, const void *data) rpc->interrupts_uninit = gen_rp_interrupts_uninit; rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET; rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET; + rpc->svc_offset = GEN_PCIE_ROOT_PORT_SVC_OFFSET; } static const TypeInfo gen_rp_dev_info = { diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index 0ae7b10fbd..9c325aa5f4 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -120,6 +120,10 @@ static void rp_realize(PCIDevice *d, Error **errp) if (rpc->acs_offset && !s->disable_acs) { pcie_acs_init(d, rpc->acs_offset); } + if (!pci_is_cxl(d) && p->svc) { + pcie_svc_cap_init(d, rpc->svc_offset, errp); + } + return; err: diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 090a3fdfc9..a2546d5060 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -110,6 +110,9 @@ static void xio3130_downstream_realize(PCIDevice *d, Error **errp) if (rc < 0) { goto err; } + if (p->svc) { + pcie_svc_cap_init(d, XIO3130_AER_OFFSET + PCI_ERR_SIZEOF, errp); + } return; diff --git a/hw/pci-bridge/xio3130_upstream.c b/hw/pci-bridge/xio3130_upstream.c index 767b7d17f2..fd15e8c943 100644 --- a/hw/pci-bridge/xio3130_upstream.c +++ b/hw/pci-bridge/xio3130_upstream.c @@ -92,6 +92,9 @@ static void xio3130_upstream_realize(PCIDevice *d, Error **errp) if (rc < 0) { goto err; } + if (p->svc) { + pcie_svc_cap_init(d, XIO3130_AER_OFFSET + PCI_ERR_SIZEOF, errp); + } return; diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index 0b3e0efb8c..8de95d71ef 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -97,6 +97,7 @@ struct PCIERootPortClass { int aer_offset; int ssvid_offset; int acs_offset; /* If nonzero, optional ACS capability offset */ + int svc_offset; /* optional SVC capability */ int ssid; }; -- 2.34.1
