Adds SVC and Dev3 capability to CXL type 3 device to make it work as a UIO completer.
Signed-off-by: Shrihari E S <[email protected]> Signed-off-by: Dongjoo Seo <[email protected]> --- hw/mem/cxl_type3.c | 15 +++++++++++++++ include/hw/cxl/cxl_device.h | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 0adf2e8b3e..74ddcf6e58 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1195,6 +1195,20 @@ void ct3_realize(PCIDevice *pci_dev, Error **errp) pcie_doe_init(pci_dev, &ct3d->doe_comp, 0x1b0, doe_comp_prot, true, CXL_T3_MSIX_PCIE_DOE_COMPLIANCE); + if (ct3d->svc) { + /* SVC capability of the type3 device */ + rc = pcie_svc_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF, errp); + if ((rc >= 0) && ct3d->flitmode && ct3d->uio_comp_capable) { + + /* + * The Dev3 Capability is initialized after AER in the PCIe config + * space. Also initializing CXL type3 device as a UIO completer. + */ + pcie_dev3_cap_init(pci_dev, 0x200 + PCI_ERR_SIZEOF + PCI_SVC_SIZEOF, + false, true, errp); + } + } + /* Set default value for patrol scrub attributes */ ct3d->patrol_scrub_attrs.scrub_cycle_cap = CXL_MEMDEV_PS_SCRUB_CYCLE_CHANGE_CAP_DEFAULT | @@ -1560,6 +1574,7 @@ static const Property ct3_props[] = { width, PCIE_LINK_WIDTH_16), DEFINE_PROP_BOOL("x-256b-flit", CXLType3Dev, flitmode, false), DEFINE_PROP_BOOL("hdm-db", CXLType3Dev, hdmdb, false), + DEFINE_PROP_BOOL("x-svc", CXLType3Dev, svc, false), DEFINE_PROP_BOOL("x-uio", CXLType3Dev, uio_comp_capable, false), DEFINE_PROP_UINT16("chmu-port", CXLType3Dev, cxl_dstate.chmu[0].port, 0), }; diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 3d92d3f46c..5505aefe37 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -885,6 +885,7 @@ struct CXLType3Dev { bool flitmode; bool uio_comp_capable; bool uio_enabled; + bool svc; /* DOE */ DOECap doe_cdat; -- 2.34.1
