Add a command-line example demonstrating a topology with three CXL Type-3 devices connected via a switch. This example enables Unordered I/O (UIO) on all ports and endpoints to illustrate the correct usage of UIO-related properties.
Signed-off-by: Shrihari E S <[email protected]> Signed-off-by: Dongjoo Seo <[email protected]> --- docs/system/devices/cxl.rst | 47 +++++++++++++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/docs/system/devices/cxl.rst b/docs/system/devices/cxl.rst index 32b1b5d773..378fb5b2c1 100644 --- a/docs/system/devices/cxl.rst +++ b/docs/system/devices/cxl.rst @@ -407,6 +407,53 @@ use HDM-DB for coherence, which requires operating in Flit mode:: -device cxl-type3,bus=swport3,volatile-memdev=cxl-mem3,id=cxl-mem3,sn=0x4 \ -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k +Unordered I/O (UIO) Support +--------------------------- +CXL 3.2 and PCIe 6.1 introduce Unordered I/O (UIO), which allows memory +transactions to bypass strict ordering requirements, potentially improving +performance for certain workloads. UIO support requires three coordinated +features: + +1. **256-byte Flit Mode**: Enabled via ``x-256b-flit=on`` on all ports + and devices in the UIO path +2. **Streamlined Virtual Channel (SVC)**: Enabled via ``x-svc`` on all ports + and CXL type3 device. SVC is a PCIe 6.1 extended capability + (PCIe 6.4 section 7.9.29) that provides dedicated virtual channels for + UIO traffic. +3. **Device 3 Extended Capability**: Enabled via ``x-uio`` on CXL type3 + device. Device3 is a PCIe 6.4 extended capability (PCIe 6.4 section 7.7.9) + that advertises a device's UIO requester/completer support. + +An example of 3 type3 devices with volatile memory below a switch. All the devices +and ports support Unordered IO (UIO) feature which requires Streamlined Virtual Channel +(SVC) capability, Device3 capability and requires operating in Flit mode:: + + qemu-system-x86_64 -M q35,cxl=on -m 4G,maxmem=8G,slots=8 -smp 4 \ + ... + -object memory-backend-ram,id=target-mem1,size=512M \ + -object memory-backend-ram,id=target-mem2,size=512M \ + -object memory-backend-ram,id=target-mem3,size=512M \ + -device pxb-cxl,bus_nr=12,bus=pcie.0,id=cxl.1 \ + -device cxl-rp,port=0,bus=cxl.1,id=rp13,chassis=0,slot=0,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-rp,port=1,bus=cxl.1,id=root_port1,chassis=0,slot=1,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-upstream,port=2,sn=1234,bus=rp13,id=us0,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-downstream,port=0,bus=us0,id=swport0,chassis=0,slot=4,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-downstream,port=1,bus=us0,id=swport1,chassis=0,slot=5,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-downstream,port=3,bus=us0,id=swport2,chassis=0,slot=6,\ + x-svc=on,x-256b-flit=on,x-speed=64,x-width=16 \ + -device cxl-type3,id=mem1,bus=swport0,volatile-memdev=target-mem1,\ + x-uio=on,x-svc=on,x-256b-flit=on,sn=1233 \ + -device cxl-type3,id=mem2,bus=swport1,volatile-memdev=target-mem2,\ + x-uio=on,x-svc=on,x-256b-flit=on,sn=1234 \ + -device cxl-type3,id=mem3,bus=swport2,volatile-memdev=target-mem3,\ + x-uio=on,x-svc=on,x-256b-flit=on,sn=1235 \ + -M cxl-fmw.0.targets.0=cxl.1,cxl-fmw.0.size=4G,cxl-fmw.0.interleave-granularity=4k + A simple arm/virt example featuring a single direct connected CXL Type 3 Volatile Memory device:: -- 2.34.1
