Hi Shrihari, On Wed, 26 Aug 2026 11:04:10 +0530, Shrihari E S wrote: > +3. **Device 3 Extended Capability**: Enabled via ``x-uio`` on CXL type3
x-uio on its own doesn't get you Dev3: ct3_realize() adds it only when x-svc and x-256b-flit are set as well. It does set the HDM UIO bit with neither of them, which is the asymmetry I raised on 9/10. > +An example of 3 type3 devices with volatile memory below a switch. All the > devices > +and ports support Unordered IO (UIO) feature which requires Streamlined > Virtual Channel The topology below this doesn't advertise UIO through the switch. I ran it -- joined onto single lines, the indented continuations don't survive a paste -- and the upstream port reads 0x00000382 in its HDM Decoder Capability register, UIO clear, against 0x00042312 on cxl-rp. That's the gate in 7/10; worth re-running the example once it's settled. Many thanks, Junjie
