On Wed, 2026-08-26 at 20:44 +0900, [email protected] wrote: > > It is true that the current behavior differs from the pseudocode in the > manual. > Wouldn't it be simpler to just generate a TCG that matches the pseudocode? > I'm sorry, I haven't actually tested this change yet. > > diff --git a/target/sh4/translate.c b/target/sh4/translate.c > index e503a97b22..64fe2cd31d 100644 > --- a/target/sh4/translate.c > +++ b/target/sh4/translate.c > @@ -801,13 +801,13 @@ static void _decode_opc(DisasContext * ctx) > { > TCGv arg0, arg1; > arg0 = tcg_temp_new(); > - tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > - MO_TESL | MO_ALIGN); > - tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); > arg1 = tcg_temp_new(); > tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, > MO_TESL | MO_ALIGN); > tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); > + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > + MO_TESL | MO_ALIGN); > + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); > gen_helper_macl(tcg_env, arg0, arg1); > } > return; > @@ -815,13 +815,13 @@ static void _decode_opc(DisasContext * ctx) > { > TCGv arg0, arg1; > arg0 = tcg_temp_new(); > - tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > - MO_TESW | MO_ALIGN); > - tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); > arg1 = tcg_temp_new(); > tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, > MO_TESW | MO_ALIGN); > tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); > + tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, > + MO_TESW | MO_ALIGN); > + tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); > gen_helper_macw(tcg_env, arg0, arg1); > } > return; > >
Thanks, I think you're right. I'll have another look and report back in a few days. Best regards, Oleg Endo
