Add the const qualifier to CPULoongArchState when
the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
---
target/loongarch/cpu-mmu.h | 20 ++++++++++----------
target/loongarch/tcg/tcg_loongarch.h | 2 +-
target/loongarch/cpu_helper.c | 20 ++++++++++----------
target/loongarch/tcg/tlb_helper.c | 26 +++++++++++++-------------
4 files changed, 34 insertions(+), 34 deletions(-)
diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h
index 54fb732d62d..61b59f3d3f3 100644
--- a/target/loongarch/cpu-mmu.h
+++ b/target/loongarch/cpu-mmu.h
@@ -30,14 +30,14 @@ typedef struct MMUContext {
uint64_t pte_buddy[2];
} MMUContext;
-static inline bool cpu_has_ptw(CPULoongArchState *env)
+static inline bool cpu_has_ptw(const CPULoongArchState *env)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
return !!FIELD_EX64(sys->CSR_PWCH, CSR_PWCH, HPTW_EN);
}
-static inline bool pte_present(CPULoongArchState *env, uint64_t entry)
+static inline bool pte_present(const CPULoongArchState *env, uint64_t entry)
{
uint8_t present;
@@ -50,7 +50,7 @@ static inline bool pte_present(CPULoongArchState *env, uint64_t entry)
return !!present;
}
-static inline bool pte_write(CPULoongArchState *env, uint64_t entry)
+static inline bool pte_write(const CPULoongArchState *env, uint64_t entry)
{
uint8_t writable;
@@ -89,17 +89,17 @@ static inline bool pte_dirty(uint64_t entry)
return !!FIELD_EX64(entry, TLBENTRY, D);
}
-bool check_ps(CPULoongArchState *ent, uint8_t ps);
-TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+bool check_ps(const CPULoongArchState *ent, uint8_t ps);
+TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx);
-TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
+TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug);
-TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context,
int access_type, int mmu_idx, int debug);
-void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, unsigned int level);
hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
-uint64_t loongarch_palen_mask(CPULoongArchState *env);
+uint64_t loongarch_palen_mask(const CPULoongArchState *env);
#endif /* LOONGARCH_CPU_MMU_H */
diff --git a/target/loongarch/tcg/tcg_loongarch.h
b/target/loongarch/tcg/tcg_loongarch.h
index 7fb627f2d63..0f20c60d73d 100644
--- a/target/loongarch/tcg/tcg_loongarch.h
+++ b/target/loongarch/tcg/tcg_loongarch.h
@@ -16,7 +16,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int
size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx);
diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c
index 123cad3d930..3401e7ed727 100644
--- a/target/loongarch/cpu_helper.c
+++ b/target/loongarch/cpu_helper.c
@@ -18,10 +18,10 @@
#include "cpu-mmu.h"
#include "tcg/tcg_loongarch.h"
-void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base,
+void get_dir_base_width(const CPULoongArchState *env, uint64_t *dir_base,
uint64_t *dir_width, unsigned int level)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
switch (level) {
case 1:
@@ -48,7 +48,7 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t
*dir_base,
}
}
-TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_check_pte(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx)
{
uint64_t plv = mmu_idx;
@@ -111,7 +111,7 @@ TLBRet loongarch_check_pte(CPULoongArchState *env,
MMUContext *context,
return TLBRET_MATCH;
}
-static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys,
+static MemTxResult loongarch_cmpxchg_phys(const CPUState *cs, hwaddr phys,
uint64_t old, uint64_t new)
{
hwaddr addr1, l = 8;
@@ -146,11 +146,11 @@ static MemTxResult loongarch_cmpxchg_phys(CPUState *cs,
hwaddr phys,
return ret;
}
-TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context,
+TLBRet loongarch_ptw(const CPULoongArchState *env, MMUContext *context,
int access_type, int mmu_idx, int debug)
{
const MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED;
- CPUState *cs = env_cpu(env);
+ const CPUState *cs = env_cpu(env);
hwaddr index = 0, phys = 0;
uint64_t palen_mask = loongarch_palen_mask(env);
uint64_t dir_base, dir_width;
@@ -273,7 +273,7 @@ restart:
return ret;
}
-static TLBRet loongarch_map_address(CPULoongArchState *env,
+static TLBRet loongarch_map_address(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
@@ -299,7 +299,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *env,
return TLBRET_NOMATCH;
}
-static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va, uint64_t dmw)
+static hwaddr dmw_va2pa(const CPULoongArchState *env, vaddr va, uint64_t dmw)
{
if (is_la64(env)) {
return va & TARGET_VIRT_MASK;
@@ -310,7 +310,7 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, vaddr va,
uint64_t dmw)
}
}
-TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context,
+TLBRet get_physical_address(const CPULoongArchState *env, MMUContext *context,
MMUAccessType access_type, int mmu_idx,
int is_debug)
{
@@ -376,7 +376,7 @@ hwaddr loongarch_cpu_get_phys_addr_debug(CPUState *cs,
vaddr addr)
return context.physical;
}
-uint64_t loongarch_palen_mask(CPULoongArchState *env)
+uint64_t loongarch_palen_mask(const CPULoongArchState *env)
{
/* PALEN stores physical address bits - 1 */
uint64_t phys_bits = FIELD_EX32(env->cpucfg[1], CPUCFG1, PALEN) + 1;
diff --git a/target/loongarch/tcg/tlb_helper.c
b/target/loongarch/tcg/tlb_helper.c
index a4b90beca65..6194b976c36 100644
--- a/target/loongarch/tcg/tlb_helper.c
+++ b/target/loongarch/tcg/tlb_helper.c
@@ -35,9 +35,9 @@ static bool tlb_match_asid(bool global, int asid, int
tlb_asid)
return !global && tlb_asid == asid;
}
-bool check_ps(CPULoongArchState *env, uint8_t tlb_ps)
+bool check_ps(const CPULoongArchState *env, uint8_t tlb_ps)
{
- CPUSysState *sys = env_sys(env);
+ const CPUSysState *sys = env_sys(env);
if (tlb_ps >= 64) {
return false;
@@ -238,11 +238,11 @@ static uint32_t get_random_tlb(uint32_t low, uint32_t
high)
* field in tlb entry contains bit[47:13], so need adjust.
* virt_vpn = vaddr[47:13]
*/
-static LoongArchTLB *loongarch_tlb_search_cb(CPULoongArchState *env,
- vaddr vaddr, int csr_asid,
- tlb_match func)
+static const LoongArchTLB *
+loongarch_tlb_search_cb(const CPULoongArchState *env, vaddr vaddr,
+ int csr_asid, tlb_match func)
{
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
uint16_t tlb_asid, stlb_idx;
uint8_t tlb_e, tlb_ps, stlb_ps;
bool tlb_g;
@@ -291,12 +291,12 @@ static LoongArchTLB
*loongarch_tlb_search_cb(CPULoongArchState *env,
return NULL;
}
-static bool loongarch_tlb_search(CPULoongArchState *env, vaddr vaddr,
+static bool loongarch_tlb_search(const CPULoongArchState *env, vaddr vaddr,
int *index)
{
int csr_asid;
tlb_match func;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
CPUSysState *sys = env_sys(env);
func = tlb_match_any;
@@ -594,7 +594,7 @@ void helper_invtlb_page_asid(CPULoongArchState *env,
target_ulong info,
target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_asid;
@@ -608,7 +608,7 @@ void helper_invtlb_page_asid_or_g(CPULoongArchState *env,
target_ulong info, target_ulong addr)
{
int asid = info & 0x3ff;
- LoongArchTLB *tlb;
+ const LoongArchTLB *tlb;
tlb_match func;
func = tlb_match_any;
@@ -837,12 +837,12 @@ void helper_ldpte(CPULoongArchState *env, target_ulong
base, target_ulong odd,
sys->CSR_TLBREHI = FIELD_DP64(sys->CSR_TLBREHI, CSR_TLBREHI, PS, ps);
}
-static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env,
+static TLBRet loongarch_map_tlb_entry(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int index,
int mmu_idx)
{
- LoongArchTLB *tlb = &env->tlb[index];
+ const LoongArchTLB *tlb = &env->tlb[index];
uint8_t tlb_ps, n;
tlb_ps = FIELD_EX64(tlb->tlb_misc, TLB_MISC, PS);
@@ -853,7 +853,7 @@ static TLBRet loongarch_map_tlb_entry(CPULoongArchState
*env,
return loongarch_check_pte(env, context, access_type, mmu_idx);
}
-TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env,
+TLBRet loongarch_get_addr_from_tlb(const CPULoongArchState *env,
MMUContext *context,
MMUAccessType access_type, int mmu_idx)
{
