Instantiate all four standard Cadence GEM controllers described by the E2000 SoC device tree. The generic model implements the first 0x800 bytes of each 0x2000-byte E2000 aperture, so cover the complete window with a low-priority unimplemented region and map the Cadence registers on top. This accepts accesses to the SoC-specific clock and SerDes selectors without inventing their behavior.
Connect eight queue interrupts for GEM0 and four for GEM1 through GEM3, and configure the PCS, MDIO PHY address and 16360-byte jumbo limit expected by the SDK drivers. Signed-off-by: Bin Meng <[email protected]> --- hw/arm/Kconfig | 1 + hw/arm/phytium_e2000.c | 62 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 63 insertions(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 9358a47b8a..08128232ca 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -132,6 +132,7 @@ config PHYTIUM_E2000 depends on TCG && AARCH64 imply PCI_DEVICES select ARM_GIC + select CADENCE select DW_MCI select PCI_EXPRESS select PCI_EXPRESS_GENERIC_BRIDGE diff --git a/hw/arm/phytium_e2000.c b/hw/arm/phytium_e2000.c index 88307184e9..c68a565330 100644 --- a/hw/arm/phytium_e2000.c +++ b/hw/arm/phytium_e2000.c @@ -26,10 +26,12 @@ #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" #include "hw/misc/unimp.h" +#include "hw/net/cadence_gem.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" #include "hw/sd/phytium_e2000_mci.h" #include "hw/sd/sd.h" +#include "net/net.h" #include "qobject/qlist.h" #include "qom/object.h" #include "target/arm/cpu.h" @@ -44,6 +46,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(PhytiumE2000State, PHYTIUM_PI) #define PHYTIUM_E2000_NUM_MCIS 2 #define PHYTIUM_E2000_NUM_UARTS 7 +#define PHYTIUM_E2000_NUM_GEMS 4 #define PHYTIUM_E2000_GTIMER_HZ 50000000 @@ -65,6 +68,10 @@ enum { PHYTIUM_E2000_PCIE_CTRL, PHYTIUM_E2000_PCIE_PHY_CTRL, PHYTIUM_E2000_BOARD_CTRL, + PHYTIUM_E2000_GEM0, + PHYTIUM_E2000_GEM1, + PHYTIUM_E2000_GEM2, + PHYTIUM_E2000_GEM3, PHYTIUM_E2000_BOOT_IACC, PHYTIUM_E2000_PCIE_ECAM, PHYTIUM_E2000_PCIE_PIO, @@ -79,6 +86,7 @@ struct PhytiumE2000State { struct arm_boot_info bootinfo; DeviceState *gic; PhytiumE2000MciState *mci[PHYTIUM_E2000_NUM_MCIS]; + CadenceGEMState *gem[PHYTIUM_E2000_NUM_GEMS]; MemoryRegion ram_low; MemoryRegion ram_high; }; @@ -106,6 +114,10 @@ static const MemMapEntry phytium_e2000_memmap[] = { [PHYTIUM_E2000_PCIE_CTRL] = { 0x31000000, 0x00200000 }, [PHYTIUM_E2000_PCIE_PHY_CTRL] = { 0x31500000, 0x00001000 }, [PHYTIUM_E2000_BOARD_CTRL] = { 0x31800000, 0x01400000 }, + [PHYTIUM_E2000_GEM0] = { 0x3200c000, 0x00002000 }, + [PHYTIUM_E2000_GEM1] = { 0x3200e000, 0x00002000 }, + [PHYTIUM_E2000_GEM2] = { 0x32010000, 0x00002000 }, + [PHYTIUM_E2000_GEM3] = { 0x32012000, 0x00002000 }, [PHYTIUM_E2000_BOOT_IACC] = { 0x38000000, 0x08000000 }, [PHYTIUM_E2000_PCIE_ECAM] = { 0x40000000, 0x10000000 }, [PHYTIUM_E2000_PCIE_PIO] = { 0x50000000, 0x00f00000 }, @@ -130,6 +142,16 @@ static const int phytium_e2000_uart_irqmap[] = { [6] = 107, }; +static const uint8_t phytium_e2000_gem_num_queues[] = { 8, 4, 4, 4 }; + +static const int phytium_e2000_gem_irqmap[PHYTIUM_E2000_NUM_GEMS] + [MAX_PRIORITY_QUEUES] = { + [0] = { 55, 56, 57, 58, 28, 29, 30, 31 }, + [1] = { 59, 60, 61, 62 }, + [2] = { 64, 65, 66, 67 }, + [3] = { 68, 69, 70, 71 }, +}; + static const int phytium_e2000_pcie_irqmap[PCI_NUM_PINS] = { [0] = 4, [1] = 5, @@ -255,6 +277,43 @@ static void phytium_e2000_create_uart(PhytiumE2000State *s, int index) qdev_get_gpio_in(s->gic, phytium_e2000_uart_irqmap[index])); } +static void phytium_e2000_create_gem(PhytiumE2000State *s, int index) +{ + DeviceState *dev = qdev_new(TYPE_CADENCE_GEM); + CadenceGEMState *gem = CADENCE_GEM(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + g_autofree char *name = g_strdup_printf("gem%d", index); + g_autofree char *unimp_name = + g_strdup_printf("phytium-e2000.gem%d-unimplemented", index); + int map_idx = PHYTIUM_E2000_GEM0 + index; + hwaddr base = phytium_e2000_memmap[map_idx].base; + int i; + + s->gem[index] = gem; + object_property_add_child(OBJECT(s), name, OBJECT(dev)); + + qemu_configure_nic_device(dev, true, name); + qdev_prop_set_uint8(dev, "phy-addr", 0); + qdev_prop_set_uint8(dev, "num-priority-queues", + phytium_e2000_gem_num_queues[index]); + qdev_prop_set_uint16(dev, "jumbo-max-len", 16360); + qdev_prop_set_bit(dev, "pcs-enabled", true); + + /* + * The E2000 exposes a 0x2000-byte aperture, while the generic Cadence + * model implements the first 0x800 bytes. Catch accesses to the remaining + * SoC-specific registers without inventing their clock and SerDes effects. + */ + create_unimplemented_device(unimp_name, base, + phytium_e2000_memmap[map_idx].size); + sysbus_realize_and_unref(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, base); + for (i = 0; i < phytium_e2000_gem_num_queues[index]; i++) { + sysbus_connect_irq(sbd, i, + qdev_get_gpio_in(s->gic, phytium_e2000_gem_irqmap[index][i])); + } +} + /* The vendor DT maps root-bus INTx solely by pin */ static int phytium_e2000_pcie_map_irq(PCIDevice *pdev, int pin) { @@ -511,6 +570,9 @@ static void phytium_pi_init(MachineState *ms) for (i = 0; i < PHYTIUM_E2000_NUM_UARTS; i++) { phytium_e2000_create_uart(s, i); } + for (i = 0; i < PHYTIUM_E2000_NUM_GEMS; i++) { + phytium_e2000_create_gem(s, i); + } phytium_e2000_create_pcie(s); -- 2.53.0
