From: Alistair Francis <[email protected]> The following changes since commit 99e54ab5e7a6efc945af6d5661842155d1f3fc7a:
Merge tag 'hw-misc-20260903' of https://github.com/philmd/qemu into staging (2026-09-03 16:43:24 +0100) are available in the Git repository at: https://github.com/alistair23/qemu.git tags/pull-riscv-to-apply-20260904 for you to fetch changes up to b23a62773a7856299cbb3782e64968b6a92c792f: hw/riscv/atlantis: Map the SoC through a memory container (2026-09-04 10:30:14 +1000) ---------------------------------------------------------------- RISC-V PR for 11.2 * Add initial sdext support * Make RISCVBootInfo const where possible * Use hwaddr for virt IMSIC device tree address * Avoid unnecessary removal of test scratch files * Document Atlantis QEMU-only I2C device tree nodes * Make s-mode IMSIC stride explicit * Correct dasm for cbo and lq * Add tests for rv128 [ms]status * Code duplication work in preperation for riscv-server-ref * Fix user option hash table leaks * Preserve vl on element-zero fault * Prevent abrupt abortion on unassigned value write to tdata * Socify Atlantis ---------------------------------------------------------------- Abhigyan Kumar (1): target/riscv: prevent abrupt abortion on unassigned value write to tdata Daniel Henrique Barboza (20): target/riscv: split 'debug' and 'sdtrig' flags target/riscv/tcg/debug.c: add Debug 1.0 'pending' bit target/riscv/tcg/debug: adjust 'timing' bit for Debug 1.0 target/riscv/tcg/debug: set tinfo version if sdtrig enabled docs/specs: add RISC-V CPU Debug support info hw/riscv/fdt-common: prepend helpers with "riscv_" hw/riscv/fdt-common, virt.c: add riscv_create_fdt_flash() hw/riscv/fdt-common, virt.c: add riscv_create_fdt_syscon() hw/riscv/fdt-common, virt.c: add riscv_create_fdt_riscv_iommu_sys() hw/riscv/fdt_common, virt.c: add riscv_create_fdt_pcie() hw/riscv/fdt_common, virt.c: add riscv_create_fdt_imsic() hw/riscv/fdt_common, virt.c: add riscv_create_fdt_socket_aplic() hw/riscv/virt.c: fix aclint soc/mtimer nodename hw/riscv/fdt-common, virt.c: add riscv_create_fdt_socket_aclint() hw/riscv/fdt-common, virt.c: add riscv_create_fdt_uart() hw/riscv/fdt-common, virt.c: add riscv_create_fdt_rtc() hw/riscv/device-common, virt.c: add riscv_create_platform_bus() hw/riscv/device-common, virt.c: add flash helpers hw/riscv/device-common, virt.c: add riscv_gpex_pcie_init() hw/riscv/riscv-iommu-sys.c, virt.c: add riscv_create_iommu_sys() Frédéric Pétrot (2): disas/riscv.c: Correct dasm for cbo and lq tests/tcg/riscv64: Add tests for rv128 [ms]status Joel Stanley (21): hw/riscv/boot: Make RISCVBootInfo const where possible hw/riscv/virt: Use hwaddr for IMSIC device tree address tests/functional: Avoid unnecessary removal of scratch files hw/riscv/atlantis: Document QEMU-only I2C device tree nodes hw/riscv: Make s-mode IMSIC stride explicit hw/riscv/aia: Check for invalid IMSIC configs hw/riscv/aia: Take a MemoryRegion for the created devices hw/intc/riscv_aclint: Take a MemoryRegion for the created devices hw/intc/riscv_imsic: Take a MemoryRegion for the created device hw/intc/riscv_aplic: Take a MemoryRegion for the created device hw/intc/sifive_plic: Take a MemoryRegion for the created device hw/riscv/cps: Map interrupt controllers in SoC container hw/riscv/atlantis: Make UART unimp region a SoC device hw/riscv/atlantis: Remove unused fdt_size hw/riscv/atlantis: Rename hart array 'soc' to 'cpus' hw/riscv/atlantis: Rework device tree creation hw/riscv/atlantis: Use local reference for system memory hw/riscv/atlantis: Decouple RAM size from MachineState hw/riscv/atlantis: Make TTAtlantisState own memory containers hw/riscv/atlantis: Extract an Atlantis SoC device hw/riscv/atlantis: Map the SoC through a memory container Portia Stephens (1): hw/riscv: Add property to hart array to allow private memory TANG Tiancheng (1): target/riscv/tcg: fix user option hash table leaks Zephyr Li (1): target/riscv: preserve vl on element-zero fault docs/specs/index.rst | 1 + docs/specs/riscv-debug.rst | 68 +++ hw/riscv/aia.h | 4 +- hw/riscv/riscv-iommu.h | 3 + include/hw/intc/riscv_aclint.h | 7 +- include/hw/intc/riscv_aplic.h | 7 +- include/hw/intc/riscv_imsic.h | 3 +- include/hw/intc/sifive_plic.h | 4 +- include/hw/riscv/boot.h | 6 +- include/hw/riscv/device-common.h | 32 ++ include/hw/riscv/fdt-common.h | 146 ++++- include/hw/riscv/riscv_hart.h | 2 + include/hw/riscv/tt_atlantis.h | 32 +- include/hw/riscv/virt.h | 15 - target/riscv/cpu.h | 2 + target/riscv/tcg/debug.h | 6 +- target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn32.decode | 2 + disas/riscv.c | 20 +- hw/intc/riscv_aclint.c | 12 +- hw/intc/riscv_aplic.c | 10 +- hw/intc/riscv_imsic.c | 6 +- hw/intc/sifive_plic.c | 7 +- hw/riscv/aia.c | 24 +- hw/riscv/boot.c | 6 +- hw/riscv/cps.c | 12 +- hw/riscv/device-common.c | 168 ++++++ hw/riscv/fdt-common.c | 613 ++++++++++++++++++++- hw/riscv/k230.c | 9 +- hw/riscv/microchip_pfsoc.c | 8 +- hw/riscv/riscv-iommu-sys.c | 25 + hw/riscv/riscv_hart.c | 8 + hw/riscv/shakti_c.c | 10 +- hw/riscv/sifive_e.c | 6 +- hw/riscv/sifive_u.c | 44 +- hw/riscv/spike.c | 34 +- hw/riscv/tt_atlantis.c | 310 +++++++---- hw/riscv/virt.c | 883 +++++------------------------- hw/riscv/xiangshan_kmh.c | 17 +- target/riscv/cpu.c | 23 +- target/riscv/machine.c | 2 +- target/riscv/tcg/csr.c | 2 +- target/riscv/tcg/debug.c | 54 +- target/riscv/tcg/tcg-cpu.c | 57 +- target/riscv/tcg/vector_helper.c | 23 +- hw/riscv/meson.build | 1 + tests/functional/arm/test_bpim2u.py | 11 - tests/functional/arm/test_orangepi.py | 9 - tests/functional/riscv64/test_sifive_u.py | 4 - tests/tcg/riscv64/Makefile.softmmu-target | 14 + tests/tcg/riscv64/test-rv128-mstatus.S | 67 +++ tests/tcg/riscv64/test-rv128-sstatus.S | 108 ++++ tests/tcg/riscv64/test-vle32ff.S | 58 ++ 53 files changed, 1906 insertions(+), 1100 deletions(-) create mode 100644 docs/specs/riscv-debug.rst create mode 100644 include/hw/riscv/device-common.h create mode 100644 hw/riscv/device-common.c create mode 100644 tests/tcg/riscv64/test-rv128-mstatus.S create mode 100644 tests/tcg/riscv64/test-rv128-sstatus.S create mode 100644 tests/tcg/riscv64/test-vle32ff.S
