On Mon, Sep 07, 2026 at 05:37:28PM +0800, Chen Pei wrote:
> Enable CXL support on the RISC-V virt machine following the same
> approach used by the ARM virt machine:
> - Add PXB and ACPI_CXL Kconfig selections
> - Add CXLState and PCIBus pointer to RISCVVirtState
> - Register CXL machine properties via cxl_machine_init()
> - Create CXL host register region above the PCIe high MMIO region
> - Call cxl_hook_up_pxb_registers() and cxl_fmws_link_targets() at
> machine_done time
> - Map Fixed Memory Windows above the CXL host register region
> - Add ACPI0017 device in DSDT and build CEDT table in virt-acpi-build.c
>
> Reviewed-by: Junjie Cao <[email protected]>
> Tested-by: Junjie Cao <[email protected]>
> Signed-off-by: Chen Pei <[email protected]>
Reviewed-by: Chao Liu <[email protected]>
Thanks,
Chao
> ---
> hw/riscv/Kconfig | 2 ++
> hw/riscv/virt-acpi-build.c | 20 ++++++++++++++++
> hw/riscv/virt.c | 47 ++++++++++++++++++++++++++++++++++----
> include/hw/riscv/virt.h | 3 +++
> 4 files changed, 68 insertions(+), 4 deletions(-)
>
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index d06ac26648..c2f8c5d2da 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconfig
> @@ -66,8 +66,10 @@ config RISCV_VIRT
> select VIRTIO_MMIO
> select FW_CFG_DMA
> select PLATFORM_BUS
> + select PXB
> select ACPI
> select ACPI_PCI
> + select ACPI_CXL
>
> config SHAKTI_C
> bool
> diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
> index 8e516ec114..2be8c6d572 100644
> --- a/hw/riscv/virt-acpi-build.c
> +++ b/hw/riscv/virt-acpi-build.c
> @@ -29,12 +29,16 @@
> #include "hw/acpi/aml-build.h"
> #include "hw/acpi/pci.h"
> #include "hw/acpi/utils.h"
> +#include "hw/acpi/cxl.h"
> #include "hw/intc/riscv_aclint.h"
> #include "hw/nvram/fw_cfg_acpi.h"
> #include "hw/pci-host/gpex.h"
> +#include "hw/pci/pci_bus.h"
> #include "hw/riscv/virt.h"
> #include "hw/riscv/numa.h"
> #include "hw/virtio/virtio-acpi.h"
> +#include "hw/cxl/cxl.h"
> +#include "hw/cxl/cxl_host.h"
> #include "kvm/kvm_riscv.h"
> #include "migration/vmstate.h"
> #include "qapi/error.h"
> @@ -518,6 +522,17 @@ static void build_dsdt(GArray *table_data,
> acpi_dsdt_add_gpex_host(scope, PCIE_IRQ + s->num_sources * 2);
> }
>
> + if (s->cxl_devices_state.is_enabled) {
> + Aml *cxl_dev = aml_device("CXLM");
> + aml_append(cxl_dev, aml_name_decl("_HID", aml_string("ACPI0017")));
> + Aml *method = aml_method("_STA", 0, AML_NOTSERIALIZED);
> + aml_append(method, aml_return(aml_int(0x0B)));
> + aml_append(cxl_dev, method);
> + build_cxl_dsm_method(cxl_dev);
> +
> + aml_append(scope, cxl_dev);
> + }
> +
> aml_append(dsdt, scope);
>
> /* copy AML table into ACPI tables blob and patch header there */
> @@ -925,6 +940,11 @@ static void virt_acpi_build(RISCVVirtState *s,
> AcpiBuildTables *tables)
> s->oem_table_id);
> }
>
> + if (s->cxl_devices_state.is_enabled) {
> + cxl_build_cedt(table_offsets, tables_blob, tables->linker,
> + s->oem_id, s->oem_table_id, &s->cxl_devices_state);
> + }
> +
> if (ms->numa_state->num_nodes > 0) {
> acpi_add_table(table_offsets, tables_blob);
> build_srat(tables_blob, tables->linker, s);
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index f3a1cc5ba3..70090ca70a 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -56,6 +56,8 @@
> #include "hw/pci/pci.h"
> #include "hw/pci-host/gpex.h"
> #include "hw/display/ramfb.h"
> +#include "hw/cxl/cxl.h"
> +#include "hw/cxl/cxl_host.h"
> #include "hw/acpi/aml-build.h"
> #include "qapi/qapi-visit-common.h"
> #include "hw/virtio/virtio-iommu.h"
> @@ -540,6 +542,29 @@ static void create_fdt(RISCVVirtState *s)
> create_fdt_pmu(s);
> }
>
> +static void cxl_host_state_init(RISCVVirtState *s)
> +{
> + MemoryRegion *sysmem = get_system_memory();
> + MemoryRegion *mr = &s->cxl_devices_state.host_mr;
> + hwaddr base;
> +
> + if (!s->cxl_devices_state.is_enabled) {
> + return;
> + }
> +
> + base = virt_high_pcie_memmap.base + virt_high_pcie_memmap.size;
> + base = ROUND_UP(base, 64 * KiB);
> +
> + memory_region_init(mr, OBJECT(s), "cxl_host_reg", 64 * KiB * 16);
> + memory_region_add_subregion(sysmem, base, mr);
> +
> + /* Map the Fixed Memory Windows above the CXL host register region. */
> + base += memory_region_size(mr);
> + base = ROUND_UP(base, 256 * MiB);
> + cxl_fmws_set_memmap(base, UINT64_MAX);
> + cxl_fmws_update_mmio();
> +}
> +
> static FWCfgState *create_fw_cfg(const MachineState *ms, hwaddr base)
> {
> FWCfgState *fw_cfg;
> @@ -625,6 +650,13 @@ static void virt_machine_done(Notifier *notifier, void
> *data)
> BlockBackend *pflash_blk0;
> RISCVBootInfo boot_info;
>
> + cxl_hook_up_pxb_registers(s->pci_bus, &s->cxl_devices_state,
> + &error_fatal);
> +
> + if (s->cxl_devices_state.is_enabled) {
> + cxl_fmws_link_targets(&error_fatal);
> + }
> +
> /*
> * An user provided dtb must include everything, including
> * dynamic sysbus devices. Our FDT needs to be finalized.
> @@ -716,6 +748,7 @@ static void virt_machine_init(MachineState *machine)
> MemoryRegion *system_memory = get_system_memory();
> MemoryRegion *mask_rom = g_new(MemoryRegion, 1);
> DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip;
> + DeviceState *gpex_dev;
> int i, base_hartid, hart_count;
> int socket_count = riscv_socket_count(machine);
>
> @@ -871,6 +904,8 @@ static void virt_machine_init(MachineState *machine)
> ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.size);
> }
>
> + cxl_host_state_init(s);
> +
> /* register system main memory (actual RAM) */
> memory_region_add_subregion(system_memory, s->memmap[VIRT_DRAM].base,
> machine->ram);
> @@ -898,10 +933,12 @@ static void virt_machine_init(MachineState *machine)
> qdev_get_gpio_in(virtio_irqchip, VIRTIO_IRQ + i));
> }
>
> - riscv_gpex_pcie_init(system_memory, pcie_irqchip,
> - &s->memmap[VIRT_PCIE_ECAM], &s->memmap[VIRT_PCIE_MMIO],
> - &virt_high_pcie_memmap, &s->memmap[VIRT_PCIE_PIO],
> - PCIE_IRQ);
> + gpex_dev = riscv_gpex_pcie_init(system_memory, pcie_irqchip,
> + &s->memmap[VIRT_PCIE_ECAM],
> + &s->memmap[VIRT_PCIE_MMIO],
> + &virt_high_pcie_memmap,
> + &s->memmap[VIRT_PCIE_PIO], PCIE_IRQ);
> + s->pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus;
>
> s->platform_bus_dev = riscv_create_platform_bus(mmio_irqchip,
> &s->memmap[VIRT_PLATFORM_BUS], VIRT_PLATFORM_BUS_IRQ,
> @@ -972,6 +1009,8 @@ static void virt_machine_instance_init(Object *obj)
> s->acpi = ON_OFF_AUTO_AUTO;
> s->iommu_sys = ON_OFF_AUTO_AUTO;
> s->num_sources = VIRT_IRQCHIP_NUM_SOURCES;
> +
> + cxl_machine_init(obj, &s->cxl_devices_state);
> }
>
> static char *virt_get_aia_guests(Object *obj, Error **errp)
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index e516898f9a..a7b74d10c6 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -24,6 +24,7 @@
> #include "hw/core/sysbus.h"
> #include "hw/block/flash.h"
> #include "hw/intc/riscv_imsic.h"
> +#include "hw/cxl/cxl.h"
>
> #define VIRT_CPUS_MAX_BITS 9
> #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS)
> @@ -66,6 +67,8 @@ struct RISCVVirtState {
> OnOffAuto iommu_sys;
> uint16_t pci_iommu_bdf;
> uint16_t num_sources;
> + CXLState cxl_devices_state;
> + PCIBus *pci_bus;
> };
>
> enum {
> --
> 2.50.1
>
