This series fixes five independent RISC-V emulation issues in the
XTheadCmo, XTheadBb, HLVX/PMP, Zicfilp, and environment-configuration
paths.
The first two patches correct XThead instruction handling. The third
adds the missing final PMP read check for HLVX. The fourth fixes
Zicfilp exception priority for tracked misaligned JALR targets. The
fifth canonicalizes reserved CBIE encoding while preserving the
defined CBIE=11 encoding.
Each patch is independently applicable and includes its own test
description and Signed-off-by line. The corresponding public QEMU
Work Items are linked in the commit messages:
XTheadCmo U-mode privilege:
https://gitlab.com/qemu-project/qemu/-/work_items/4412
XTheadBb RV32 th.srri:
https://gitlab.com/qemu-project/qemu/-/work_items/4413
HLVX.WU execute-only PMP:
https://gitlab.com/qemu-project/qemu/-/work_items/4414
Zicfilp misaligned JALR:
https://gitlab.com/qemu-project/qemu/-/work_items/4415
CBIE reserved encoding:
https://gitlab.com/qemu-project/qemu/-/work_items/4416
The series is based on d2843fbf, the first parent of current upstream
master ff1d2d19. No target/riscv path changed between those commits.
Validation performed:
- QEMU 11.1.1 baseline and patched witness replays passed.
- Every intermediate patch state built for qemu-system-riscv32,
qemu-system-riscv64, qemu-riscv32, and qemu-riscv64.
- The five patches pass checkpatch.pl and get_maintainer.pl review.
Please disregard v2 of this series. I missed QEMU's guidance to send
each new revision as a new top-level thread and to carry Reviewed-by
tags into the next revision. I apologize for missing these guidelines
and for the confusion. Please forgive the mistake.
Changes since v2:
- Resend the complete five-patch series as a fresh top-level
revision.
- Carry Daniel's Reviewed-by tags on patches 1, 2, and 4.
- Keep the code unchanged; patches 3 and 5 retain the requested
`Tested:` terminology updates.
wangyang (5):
target/riscv: enforce XTheadCmo U-mode privilege checks
target/riscv: mask RV32 XTheadBb th.srri shift amount
target/riscv: require read permission for HLVX accesses
target/riscv: prioritize Zicfilp checks for misaligned JALR
target/riscv: canonicalize reserved CBIE encoding
target/riscv/internals.h | 6 ++++
target/riscv/tcg/cpu_helper.c | 24 ++++++++++-----
target/riscv/tcg/csr.c | 29 +++++++++++++++++++
target/riscv/tcg/insn_trans/trans_rvi.c.inc | 9 +++++-
.../riscv/tcg/insn_trans/trans_xthead.c.inc | 5 ++--
target/riscv/tcg/op_helper.c | 11 ++++---
6 files changed, 67 insertions(+), 17 deletions(-)
--
2.55.0.windows.2
