When Zicfilp tracking is active, a misaligned indirect JALR target also violates the landing-pad requirement. Generate the landing-pad software-check before the generic instruction-address-misaligned exception for tracked targets, while retaining the existing exception for untracked targets.
Tested: RV64 M-mode and S-mode Zicfilp controls and misaligned targets with c=true and c=false. Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4415 Reviewed-by: Daniel Henrique Barboza <[email protected]> Signed-off-by: wangyang <[email protected]> --- target/riscv/tcg/insn_trans/trans_rvi.c.inc | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/tcg/insn_trans/trans_rvi.c.inc b/target/riscv/tcg/insn_trans/trans_rvi.c.inc index cc1b5dbbad..aa79a5ef3c 100644 --- a/target/riscv/tcg/insn_trans/trans_rvi.c.inc +++ b/target/riscv/tcg/insn_trans/trans_rvi.c.inc @@ -187,7 +187,14 @@ static bool trans_jalr(DisasContext *ctx, arg_jalr *a) if (misaligned) { gen_set_label(misaligned); - gen_exception_inst_addr_mis(ctx, target_pc); + if (ctx->fcfi_enabled && + a->rs1 != xRA && a->rs1 != xT0 && a->rs1 != xT2) { + tcg_gen_st8_i32(tcg_constant_i32(RISCV_EXCP_SW_CHECK_FCFI_TVAL), + tcg_env, offsetof(CPURISCVState, sw_check_code)); + generate_exception(ctx, RISCV_EXCP_SW_CHECK); + } else { + gen_exception_inst_addr_mis(ctx, target_pc); + } } ctx->base.is_jmp = DISAS_NORETURN; -- 2.55.0.windows.2
