On Thu, Sep 10, 2026 at 10:32 AM Brian Cain <[email protected]> wrote: > > target/hexagon is about to address its HVX register file through a > runtime base pointer rather than a constant offset from env, in order to > share one register file between several vCPUs. Split the other > gvec op families it needs like tcg_gen_gvec_{add,sub,mov,and,etc}. > > Add tcg_gen_gvec_{ssadd,sssub,usadd,ussub,mul}_var and > tcg_gen_gvec_{shri,sari}_var, plus the tcg_gen_gvec_2i_var plumbing the > immediate-shift forms are built on. > > Signed-off-by: Brian Cain <[email protected]> > --- > include/tcg/tcg-op-gvec-common.h | 31 ++++++ > tcg/tcg-op-gvec.c | 177 ++++++++++++++++++++++--------- > 2 files changed, 160 insertions(+), 48 deletions(-)
Reviewed-by: Marco Liebel <[email protected]>
