Hi Peter, Thanks, that split makes sense.
For v4 I will replace this patch with four focused changes: * gate the RBAR and RASR alias registers on ARM_FEATURE_M_MAIN, using the case layout you suggested so this also covers v8-M Baseline; * make the TEX bits RES0 for v6-M; * fix the minimum PMSAv7 region size validation for all affected profiles: v7-R, v6-M and v7-M; and * enable the existing PMSAv7 state, property, reset, migration and translation paths for non-v8 M-profile CPUs. The dedicated PMSAv8 path will remain selected first. I will retain the other condition changes that you confirmed are correct and add focused tests for the register layout and region size behavior. Thanks, Gilles
