On Sun, 6 Sept 2026 at 20:44, Gilles Grimaud
<[email protected]> wrote:
>
> Armv6-M supports no more than 32 external interrupts. Its ICTR and Active
> Bit Register locations are reserved, and Cortex-M0 implements two priority
> bits.
>
> Reject Armv6-M NVIC configurations with more than 32 external interrupts.
> Add a check-tcg test that verifies the reserved register behavior and
> priority masking on the microbit machine.
>
> Signed-off-by: Gilles Grimaud <[email protected]>
> ---
> hw/intc/armv7m_nvic.c | 7 +++
> tests/tcg/arm/system/meson.build | 6 +++
> tests/tcg/arm/system/test-armv6m-nvic.S | 70 +++++++++++++++++++++++++
> 3 files changed, 83 insertions(+)
> create mode 100644 tests/tcg/arm/system/test-armv6m-nvic.S
>
> diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
> index a7651f831e..c1ceb7450f 100644
> --- a/hw/intc/armv7m_nvic.c
> +++ b/hw/intc/armv7m_nvic.c
> @@ -2728,6 +2728,13 @@ static void armv7m_nvic_realize(DeviceState *dev,
> Error **errp)
> return;
> }
>
> + if (!arm_feature(&s->cpu->env, ARM_FEATURE_V7) &&
> + !arm_feature(&s->cpu->env, ARM_FEATURE_V8) &&
You don't need to check ARM_FEATURE_V8 here, because setting
ARM_FEATURE_V7 always implies V8.
> + s->num_irq > 32) {
> + error_setg(errp, "Armv6-M NVIC cannot exceed 32 external IRQs");
> + return;
> + }
-- PMM
