On Wed, 9 Sept 2026 at 15:42, Sebastian Ott <[email protected]> wrote: > > From: Cornelia Huck <[email protected]> > > Move handling of CCSIDR_EL1 over to the new *_IDREG_DEMUX > infrastructure. > > Note: the existing size of 16 is kept and might be extended > at a later time. > > Reviewed-by: Eric Auger <[email protected]> > Tested-by: Alireza Sanaee <[email protected]> > Signed-off-by: Cornelia Huck <[email protected]> > Signed-off-by: Sebastian Ott <[email protected]> > --- > target/arm/cpu.h | 6 ---- > target/arm/cpu-sysregs.h.inc | 1 + > hw/arm/virt.c | 19 ++++------ > hw/intc/armv7m_nvic.c | 2 +- > target/arm/cpu-max.c | 6 ++-- > target/arm/cpu64.c | 6 ++-- > target/arm/helper.c | 2 +- > target/arm/tcg/cpu32.c | 26 +++++++------- > target/arm/tcg/cpu64.c | 68 ++++++++++++++++++------------------ > 9 files changed, 63 insertions(+), 73 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 9652f8b0bf..f832cdd7e1 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -1121,10 +1121,6 @@ struct ArchCPU { > uint64_t pmceid0; > uint64_t pmceid1; > uint64_t mp_affinity; /* MP ID without feature bits */ > - /* The elements of this array are the CCSIDR values for each cache, > - * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. > - */ > - uint64_t ccsidr[16];
Something somewhere should be providing the equivalent of this documentation comment. That should also mention that currently we only support 16 indexes into CCSIDR because we don't implement separate MTE Allocation Tag caches. > uint64_t reset_cbar; > uint32_t reset_auxcr; > bool reset_hivecs; > @@ -2138,8 +2134,6 @@ FIELD(MFAR, FPA, 12, 40) > FIELD(MFAR, NSE, 62, 1) > FIELD(MFAR, NS, 63, 1) > > -QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= > R_V7M_CSSELR_INDEX_MASK); > - This change has lost this compile-time assertion that is checking that when we read from the CCSIDR we aren't using an out-of-bounds index. -- PMM
