On Wed, 9 Sept 2026 at 15:42, Sebastian Ott <[email protected]> wrote:
>
> From: Cornelia Huck <[email protected]>
>
> For some registers, we do not have a single ID register, but actually
> an array of values (e.g. CCSIDR_EL1, where the actual value is
> determined by whatever CSSELR_EL1 points to.) If we want to avoid
> using a different way to handle registers like that for every
> instance, we should provide some kind of infrastructure. Therefore,
> add accessors {GET,SET}_IDREG_DEMUX that are similar to the accessors
> we already use for regular ID registers.
>
> Tested-by: Alireza Sanaee <[email protected]>
> Suggested-by: Richard Henderson <[email protected]>
> Reviewed-by: Eric Auger <[email protected]>
> Signed-off-by: Cornelia Huck <[email protected]>
> Signed-off-by: Sebastian Ott <[email protected]>
> diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> index e3f931dba2..9652f8b0bf 100644
> --- a/target/arm/cpu.h
> +++ b/target/arm/cpu.h
> @@ -919,6 +919,18 @@ typedef struct {
> i_->idregs[REG ## _EL1_IDX]; \
> })
>
> +#define SET_IDREG_DEMUX(ISAR, REG, INDEX, VALUE) \
> + ({ \
> + ARMISARegisters *i_ = (ISAR); \
> + i_->idregs[REG ## _IDX + INDEX] = VALUE; \
> + })
> +
> +#define GET_IDREG_DEMUX(ISAR, REG, INDEX) \
> + ({ \
> + ARMISARegisters *i_ = (ISAR); \
> + i_->idregs[REG ## _IDX + INDEX]; \
> + })
Would it be reasonable to assert() in these that the INDEX is within
the range we expect it to be (i.e. >=0 and <= REG ##_IDX_LAST) ?
That would compensate for the loss of the compile-time checks
in patch 2 and the fact that static checkers won't be able to
see the intended bounds now this is just a slice of idregs[]
rather than a standalone array.
thanks
- PMM
