In the unlikely event of the architecturally valid case of using the zero register as a multiply input, this will be folded away during optimize.
Signed-off-by: Richard Henderson <[email protected]> --- target/mips/tcg/mxu_translate.c | 17 ++++++----------- 1 file changed, 6 insertions(+), 11 deletions(-) diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index 9559b8aada3..f30883f976f 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -964,18 +964,13 @@ static void gen_mxu_s32mul(DisasContext *ctx, bool mulu) rs = extract32(ctx->opcode, 16, 5); rt = extract32(ctx->opcode, 21, 5); - if (unlikely(rs == 0 || rt == 0)) { - tcg_gen_movi_i32(t0, 0); - tcg_gen_movi_i32(t1, 0); - } else { - gen_load_gpr(t0, rs); - gen_load_gpr(t1, rt); + gen_load_gpr(t0, rs); + gen_load_gpr(t1, rt); - if (mulu) { - tcg_gen_mulu2_i32(t0, t1, t0, t1); - } else { - tcg_gen_muls2_i32(t0, t1, t0, t1); - } + if (mulu) { + tcg_gen_mulu2_i32(t0, t1, t0, t1); + } else { + tcg_gen_muls2_i32(t0, t1, t0, t1); } tcg_gen_mov_i32(cpu_HI[0], t1); tcg_gen_mov_i32(cpu_LO[0], t0); -- 2.53.0
