Forthcoming tcg improvements will diagnose the passed null pointers,
with or without --enable-ubsan:
../src/target/mips/tcg/mxu_translate.c: In function ‘gen_mxu_S32MAX_S32MIN’:
../src/target/mips/tcg/mxu_translate.c:2149:13: error: argument 3 null where
non-null expected [-Werror=nonnull]
2149 | tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
| ^~~~~~~~~~~~~~~~
In file included from /home/rth/qemu/src/include/tcg/tcg-op.h:11,
from ../src/target/mips/tcg/translate.h:12,
from ../src/target/mips/tcg/mxu_translate.c:19:
/home/rth/qemu/src/include/tcg/tcg-op-common.h:166:23: note: in a call to
function ‘tcg_gen_smax_i32’ declared ‘nonnull’
166 | QEMU_ARG_NONNULL void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1,
TCGv_i32 arg2);
| ^~~~~~~~~~~~~~~~
../src/target/mips/tcg/mxu_translate.c:2151:13: error: argument 3 null where
non-null expected [-Werror=nonnull]
2151 | tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0);
| ^~~~~~~~~~~~~~~~
/home/rth/qemu/src/include/tcg/tcg-op-common.h:165:23: note: in a call to
function ‘tcg_gen_smin_i32’ declared ‘nonnull’
165 | QEMU_ARG_NONNULL void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1,
TCGv_i32 arg2);
| ^~~~~~~~~~~~~~~~
../src/target/mips/tcg/mxu_translate.c: In function ‘gen_mxu_d8sum’:
../src/target/mips/tcg/mxu_translate.c:3112:13: error: argument 2 null where
non-null expected [-Werror=nonnull]
3112 | tcg_gen_mov_i32(t4, 0);
| ^~~~~~~~~~~~~~~
/home/rth/qemu/src/include/tcg/tcg-op-common.h:178:23: note: in a call to
function ‘tcg_gen_mov_i32’ declared ‘nonnull’
178 | QEMU_ARG_NONNULL void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg);
| ^~~~~~~~~~~~~~~
../src/target/mips/tcg/mxu_translate.c:3123:13: error: argument 2 null where
non-null expected [-Werror=nonnull]
3123 | tcg_gen_mov_i32(t5, 0);
| ^~~~~~~~~~~~~~~
/home/rth/qemu/src/include/tcg/tcg-op-common.h:178:23: note: in a call to
function ‘tcg_gen_mov_i32’ declared ‘nonnull’
178 | QEMU_ARG_NONNULL void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg);
| ^~~~~~~~~~~~~~~
Mostly we need to drop all of the premature optimization vs
the zero register. In the extremely unlikely event that zero
is passed, the optimizer will clean things up.
Split out a helper for 32-bit 3-operand insns, which fixes
the smin/smax failures above.
Quite a bit more work wants doing to clean up the 16- and 8-bit
3-operand insns, but except for the one instance in d8sum, those
aren't currently causing problems.
r~
Richard Henderson (6):
target/mips/tcg: Fix zero in gen_mxu_d8sum
target/mips/tcg: Drop zero optimization in gen_mxu_s32mul
target/mips/tcg: Split out gen_mxu_logic
target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32MAX_S32MIN
target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32SLT
target/mips/tcg: Use gen_mxu_logic for gen_mxu_S32CPS
target/mips/tcg/mxu_translate.c | 265 +++++++-------------------------
1 file changed, 59 insertions(+), 206 deletions(-)
--
2.53.0
