From: Ivan Efremov <[email protected]> Add a qtest that reads the seed CSR on RV64 machine with Zkr support and verifies that the upper 32 bits are clear.
Signed-off-by: Ivan Efremov <[email protected]> Reviewed-by: Alistair Francis <[email protected]> Message-ID: <[email protected]> Signed-off-by: Alistair Francis <[email protected]> (cherry picked from commit e80cf294797870b019d31dd299328aebdfaaa76c) (Mjt: fixup in tests/qtest/riscv-csr-test.c for 10.0.x) Signed-off-by: Michael Tokarev <[email protected]> diff --git a/tests/qtest/riscv-csr-test.c b/tests/qtest/riscv-csr-test.c index ff5c29e6c6f..63274fea832 100644 --- a/tests/qtest/riscv-csr-test.c +++ b/tests/qtest/riscv-csr-test.c @@ -20,6 +20,12 @@ #define CSR_MVENDORID 0xf11 #define CSR_MISELECT 0x350 +#define CSR_SEED 0x015 + +#define SEED_OPST_MASK (UINT64_C(0x3) << 30) +#define SEED_OPST_ES16 (UINT64_C(0x2) << 30) +#define SEED_OPST_DEAD (UINT64_C(0x3) << 30) + static void run_test_csr(void) { uint64_t res; @@ -46,11 +52,31 @@ static void run_test_csr(void) qtest_quit(qts); } +static void run_test_seed_csr(void) +{ + uint64_t val = 0; + uint64_t opst; + QTestState *qts; + + qts = qtest_init("-machine virt -cpu tt-ascalon"); + + qtest_csr_call(qts, "get_csr", 0, CSR_SEED, &val); + + opst = val & SEED_OPST_MASK; + g_assert_true(opst == SEED_OPST_ES16 || + opst == SEED_OPST_DEAD); + + g_assert_cmphex(val >> 32, ==, 0); + + qtest_quit(qts); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); qtest_add_func("/cpu/csr", run_test_csr); + qtest_add_func("/cpu/csr/seed", run_test_seed_csr); return g_test_run(); } -- 2.47.3
