target/hexagon/cpu.c | 13 +++++++------
target/hexagon/cpu.h | 2 +-
target/hexagon/gen_tcg_sys.h | 2 +-
target/hexagon/helper.h | 5 +++--
target/hexagon/internal.h | 5 -----
target/hexagon/macros.h | 2 +-
target/hexagon/op_helper.c | 37 +++++++++++++++---------------------
target/hexagon/translate.c | 11 ++++++-----
8 files changed, 34 insertions(+), 43 deletions(-)
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index fad526ccfb5..0d2441b1671 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -333,7 +333,7 @@ static TCGTBCPUState hexagon_get_tb_cpu_state(CPUState *cs)
}
if (pc & PCALIGN_MASK) {
env->cause_code = HEX_CAUSE_PC_NOT_ALIGNED;
- hexagon_raise_exception_err(env, HEX_EVENT_PRECISE, pc);
+ hexagon_raise_exception_err(env, HEX_EVENT_PRECISE, pc, 0);
}
#ifndef CONFIG_USER_ONLY
@@ -711,14 +711,15 @@ static bool hexagon_tlb_fill(CPUState *cs, vaddr address,
int size,
return false;
}
raise_perm_exception(cs, address, slot, access_type, excp);
- do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
- retaddr);
+ hexagon_raise_exception_err(env, cs->exception_index,
+ env->gpr[HEX_REG_PC], retaddr);
}
if (probe) {
return false;
}
raise_tlbmiss_exception(cs, address, slot, access_type);
- do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
retaddr);
+ hexagon_raise_exception_err(env, cs->exception_index,
+ env->gpr[HEX_REG_PC], retaddr);
}
#include "hw/core/sysemu-cpu-ops.h"
@@ -761,8 +762,8 @@ void hexagon_cpu_do_unaligned_access(CPUState *cs, vaddr
addr,
CPUHexagonState *env = cpu_env(cs);
raise_misaligned_exception(cs, addr, 0, access_type);
- do_raise_exception(env, cs->exception_index, env->gpr[HEX_REG_PC],
- retaddr);
+ hexagon_raise_exception_err(env, cs->exception_index,
+ env->gpr[HEX_REG_PC], retaddr);
}
#endif
diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index b1533680bd7..e79d8000304 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -210,7 +210,7 @@ FIELD(TB_FLAGS, PCYCLE_ENABLED, 4, 1)
G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
uint32_t exception,
- uintptr_t pc);
+ vaddr pc, uintptr_t retaddr);
#ifndef CONFIG_USER_ONLY
/*
diff --git a/target/hexagon/gen_tcg_sys.h b/target/hexagon/gen_tcg_sys.h
index af5032214c4..489d2780470 100644
--- a/target/hexagon/gen_tcg_sys.h
+++ b/target/hexagon/gen_tcg_sys.h
@@ -80,7 +80,7 @@
#define fGEN_TCG_Y2_wait(SHORTCODE) \
do { \
RsV = RsV; \
- gen_helper_wait(tcg_env, tcg_constant_tl(ctx->pkt.pc)); \
+ gen_helper_hexagon_wait(tcg_env, tcg_constant_vaddr(ctx->pkt.pc)); \
} while (0)
#define fGEN_TCG_Y2_resume(SHORTCODE) \
diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h
index 71c8da4c46d..cf1b977f33c 100644
--- a/target/hexagon/helper.h
+++ b/target/hexagon/helper.h
@@ -18,7 +18,8 @@
#include "internal.h"
#include "helper_protos_generated.h.inc"
-DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
+DEF_HELPER_FLAGS_3(hexagon_raise_exception, TCG_CALL_NO_RETURN, noreturn,
+ env, i32, vaddr)
DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_3(gather_store, void, env, i32, int)
DEF_HELPER_1(commit_hvx_stores, void, env)
@@ -136,7 +137,7 @@ DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)
DEF_HELPER_3(setprio, void, env, i32, i32)
DEF_HELPER_2(start, void, env, i32)
DEF_HELPER_1(stop, void, env)
-DEF_HELPER_2(wait, void, env, i32)
+DEF_HELPER_2(hexagon_wait, void, env, vaddr)
DEF_HELPER_2(resume, void, env, i32)
DEF_HELPER_1(resched, void, env)
DEF_HELPER_3(modify_ssr, void, env, i32, i32)
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 05d1129916e..4b7a784fbc7 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -36,11 +36,6 @@ extern const char * const hexagon_sregnames[];
extern const char * const hexagon_gregnames[];
#endif
-void G_NORETURN do_raise_exception(CPUHexagonState *env,
- uint32_t exception,
- uint32_t PC,
- uintptr_t retaddr);
-
#define hexagon_cpu_mmu_enabled(env) ({ \
HexagonCPU *cpu = env_archcpu(env); \
cpu->globalregs ? \
diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index a5b9c24c6bb..4a87f6d72f1 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -637,7 +637,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int
shift)
#ifdef CONFIG_USER_ONLY
#define fTRAP(TRAPTYPE, IMM) \
do { \
- hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC); \
+ hexagon_raise_exception_err(env, HEX_EVENT_TRAP0, PC, 0); \
} while (0)
#endif
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index 0d08ac77361..715dfd3ce13 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -72,31 +72,24 @@ uint64_t HELPER(utimer)(void)
#define SF_MANTBITS 23
/* Exceptions processing helpers */
-G_NORETURN
-void do_raise_exception(CPUHexagonState *env, uint32_t exception,
- uint32_t PC, uintptr_t retaddr)
+G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
+ uint32_t exception,
+ vaddr pc, uintptr_t retaddr)
{
CPUState *cs = env_cpu(env);
- qemu_log_mask(CPU_LOG_INT, "%s: 0x%08" PRIx32 ", @ %08" PRIx32 "\n",
- __func__, exception, PC);
+ qemu_log_mask(CPU_LOG_INT, "%s: 0x%08" PRIx32 ", @ %08" VADDR_PRIx "\n",
+ __func__, exception, pc);
ASSERT_DIRECT_TO_GUEST_UNSET(env, exception);
- env->gpr[HEX_REG_PC] = PC;
- cs->exception_index = exception;
- cpu_loop_exit_restore(cs, retaddr);
-}
-
-G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
- uint32_t exception,
- uintptr_t pc)
-{
- do_raise_exception(env, exception, pc, 0);
+ env->gpr[HEX_REG_PC] = pc;
+ cpu_loop_exit_excp(cs, exception, retaddr);
}
-G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp,
- uint32_t PC)
+G_NORETURN void HELPER(hexagon_raise_exception)(CPUHexagonState *env,
+ uint32_t exception,
+ vaddr pc)
{
- hexagon_raise_exception_err(env, excp, PC);
+ hexagon_raise_exception_err(env, exception, pc, 0);
}
void log_store32(CPUHexagonState *env, target_ulong addr,
@@ -1733,7 +1726,7 @@ static void set_wait_mode(CPUHexagonState *env)
SET_SYSTEM_FIELD(env, HEX_SREG_MODECTL, MODECTL_W, thread_wait_mask);
}
-static void hexagon_wait_thread(CPUHexagonState *env, uint32_t PC)
+static void hexagon_wait_thread(CPUHexagonState *env, vaddr pc)
{
CPUState *cs;
@@ -1760,7 +1753,7 @@ static void hexagon_wait_thread(CPUHexagonState *env, uint32_t PC)
return;
}
set_wait_mode(env);
- env->wait_next_pc = PC + 4;
+ env->wait_next_pc = pc + 4;
cpu_interrupt(cs, CPU_INTERRUPT_HALT);
}
@@ -1828,12 +1821,12 @@ void HELPER(resched)(CPUHexagonState *env)
resched(env);
}
-void HELPER(wait)(CPUHexagonState *env, uint32_t PC)
+void HELPER(hexagon_wait)(CPUHexagonState *env, vaddr pc)
{
BQL_LOCK_GUARD();
if (!fIN_DEBUG_MODE(env->threadId)) {
- hexagon_wait_thread(env, PC);
+ hexagon_wait_thread(env, pc);
}
}
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index fd1de87405c..2774a01a47c 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -129,11 +129,12 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
return offset;
}
-static void gen_precise_exception(int cause, uint32_t PC)
+static void gen_precise_exception(int cause, vaddr pc)
{
tcg_gen_movi_i32(hex_cause_code, cause);
- gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
- tcg_constant_i32(PC));
+ gen_helper_hexagon_raise_exception(tcg_env,
+ tcg_constant_i32(HEX_EVENT_PRECISE),
+ tcg_constant_vaddr(pc));
}
#ifndef CONFIG_USER_ONLY
@@ -1071,11 +1072,11 @@ static void update_exec_counters(DisasContext *ctx)
*/
static void check_imprecise_exception(DisasContext *ctx)
{
- TCGv PC = tcg_constant_tl(ctx->pkt.pc);
TCGLabel *label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, hex_imprecise_exception, 0, label);
- gen_helper_raise_exception(tcg_env, hex_imprecise_exception, PC);
+ gen_helper_hexagon_raise_exception(tcg_env, hex_imprecise_exception,
+ tcg_constant_vaddr(ctx->pkt.pc));
gen_set_label(label);
}
#endif
