From: YannickV <[email protected]> Introduce ZynqMachineClass with qspi_flash_type field to allow different Zynq-based machines to specify their flash device type. The base Zynq machine defaults to n25q128.
Signed-off-by: YannickV <[email protected]> --- hw/arm/xilinx_zynq.c | 19 ++++++++++++++----- include/hw/arm/xilinx_zynq.h | 8 +++++++- 2 files changed, 21 insertions(+), 6 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index c1897ab1cf33..31d5b5e5caa5 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -117,7 +117,8 @@ static void gem_init(uint32_t base, qemu_irq irq) } static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, - bool is_qspi, int unit0) + bool is_qspi, int unit0, + const char *flash_type) { int unit = unit0; DeviceState *dev; @@ -149,7 +150,8 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, for (j = 0; j < num_ss; ++j) { DriveInfo *dinfo = drive_get(IF_MTD, 0, unit++); - flash_dev = qdev_new("n25q128"); + + flash_dev = qdev_new(flash_type); if (dinfo) { qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), @@ -201,6 +203,7 @@ static void ddr_ctrl_init(uint32_t base) static void zynq_init(MachineState *machine) { ZynqMachineState *zynq_machine = ZYNQ_MACHINE(machine); + ZynqMachineClass *zmc = ZYNQ_MACHINE_GET_CLASS(machine); MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ocm_ram = g_new(MemoryRegion, 1); DeviceState *dev, *slcr; @@ -280,9 +283,12 @@ static void zynq_init(MachineState *machine) pic[n] = qdev_get_gpio_in(dev, n); } - n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0); - n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n); - n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n); + n = zynq_init_spi_flashes(0xE0006000, pic[58 - GIC_INTERNAL], false, 0, + zmc->qspi_flash_type); + n = zynq_init_spi_flashes(0xE0007000, pic[81 - GIC_INTERNAL], false, n, + zmc->qspi_flash_type); + n = zynq_init_spi_flashes(0xE000D000, pic[51 - GIC_INTERNAL], true, n, + zmc->qspi_flash_type); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - GIC_INTERNAL]); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - GIC_INTERNAL]); @@ -458,6 +464,7 @@ static void zynq_machine_class_init(ObjectClass *oc, const void *data) NULL }; MachineClass *mc = MACHINE_CLASS(oc); + ZynqMachineClass *zmc = ZYNQ_MACHINE_CLASS(oc); ObjectProperty *prop; mc->desc = "Xilinx Zynq 7000 Platform Baseboard for Cortex-A9"; mc->init = zynq_init; @@ -471,11 +478,13 @@ static void zynq_machine_class_init(ObjectClass *oc, const void *data) "Supported boot modes:" " jtag qspi sd nor"); object_property_set_default_str(prop, "qspi"); + zmc->qspi_flash_type = "n25q128"; } static const TypeInfo zynq_machine_type = { .name = TYPE_ZYNQ_MACHINE, .parent = TYPE_MACHINE, + .class_size = sizeof(ZynqMachineClass), .class_init = zynq_machine_class_init, .instance_size = sizeof(ZynqMachineState), }; diff --git a/include/hw/arm/xilinx_zynq.h b/include/hw/arm/xilinx_zynq.h index 669c516ad150..33a68cdcd15e 100644 --- a/include/hw/arm/xilinx_zynq.h +++ b/include/hw/arm/xilinx_zynq.h @@ -12,12 +12,13 @@ #ifndef QEMU_ARM_ZYNQ_H #define QEMU_ARM_ZYNQ_H +#include "hw/core/boards.h" #include "target/arm/cpu-qom.h" #include "hw/core/qdev-clock.h" #include "hw/arm/boot.h" #define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") -OBJECT_DECLARE_SIMPLE_TYPE(ZynqMachineState, ZYNQ_MACHINE) +OBJECT_DECLARE_TYPE(ZynqMachineState, ZynqMachineClass, ZYNQ_MACHINE) #define ZYNQ_MAX_CPUS 2 @@ -29,4 +30,9 @@ struct ZynqMachineState { struct arm_boot_info bootinfo; }; +struct ZynqMachineClass { + MachineClass parent_class; + const char *qspi_flash_type; +}; + #endif /* QEMU_ARM_ZYNQ_H */ -- 2.47.3
