While preparing to enable MTTCG, audits and testing revealed gaps and bugs in our implementation.
LL/SC reservations should have been cleared at traps/exceptions. TLB accesses should hold a lock to make the operations atomic. Hexagon instructions with barrier or acquire/release semantics should emit corresponding TCG semantics. Brian Cain (5): target/hexagon: emit explicit TCG memory barriers target/hexagon: clear LL/SC reservations at context boundaries hw/hexagon: protect the shared architectural TLB target/hexagon: publish TLB updates before flushing tests/tcg/hexagon: cover LL/SC reservation clearing include/hw/hexagon/hexagon_tlb.h | 5 +++- hw/hexagon/hexagon_tlb.c | 27 ++++++++++++++++++++- linux-user/hexagon/cpu_loop.c | 4 ++++ target/hexagon/cpu.c | 3 +++ target/hexagon/hex_mmu.c | 6 ++--- target/hexagon/translate.c | 15 ++++++++++++ tests/tcg/hexagon/atomics.c | 40 ++++++++++++++++++++++++++++++++ 7 files changed, 94 insertions(+), 6 deletions(-) -- 2.34.1
