Set llsc_addr to ~0 during reset and soft reset, and whenever linux-user returns to guest code for a trap or a signal.
Reset previously left llsc_addr zero-initialized, so a store-conditional issued without a matching load-locked could match a guest address of zero. Signed-off-by: Brian Cain <[email protected]> --- linux-user/hexagon/cpu_loop.c | 4 ++++ target/hexagon/cpu.c | 3 +++ 2 files changed, 7 insertions(+) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index e4ef97a1184..e6bb3b62a9f 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -39,6 +39,10 @@ void cpu_loop(CPUHexagonState *env) cpu_exec_end(cs); qemu_process_cpu_events(cs); + if (trapnr != EXCP_ATOMIC && trapnr != EXCP_YIELD) { + env->llsc_addr = ~0; + } + switch (trapnr) { case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 1f7d8a8df70..7347a3342ce 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -411,6 +411,7 @@ void hexagon_cpu_soft_reset(CPUHexagonState *env) HexagonCPU *cpu; BQL_LOCK_GUARD(); + env->llsc_addr = ~0; env->t_sreg[HEX_SREG_SSR] = 0; hexagon_ssr_set_cause(env, HEX_CAUSE_RESET); @@ -446,6 +447,8 @@ static void hexagon_cpu_reset_hold(Object *obj, ResetType type) set_default_nan_mode(1, &env->hvx_fp_status); set_float_default_nan_pattern(0b01111111, &env->hvx_fp_status); + + env->llsc_addr = ~0; #ifndef CONFIG_USER_ONLY memset(env->t_sreg, 0, sizeof(uint32_t) * NUM_SREGS); memset(env->greg, 0, sizeof(uint32_t) * NUM_GREGS); -- 2.34.1
