On Sat, 26 Sept 2026 at 00:42, Jean-Francois Bortolotti <[email protected]> wrote: > > In Armv8-R AArch32 the shareability field of an MPU region lives in > PRBAR, not PRLAR: > > PRBAR: [31:6] BASE [5] RES0 [4:3] SH [2:1] AP [0] XN > PRLAR: [31:6] LIMIT [5:4] RES0 [3:1] AttrIndx [0] EN > > (Arm Cortex-R52 TRM 100026_0103_00_en: Tables 3-80 and 3-83 for > HPRBAR/HPRLAR, Tables 3-124 and 3-127 for PRBAR/PRLAR.) > > Without this fix, address translation instructions like ATS1HR > will return wrong value for PAR.SH. > > Signed-off-by: Jean-Francois Bortolotti <[email protected]> > --- > target/arm/ptw.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-)
Yep, this is clearly wrong, maybe a cut-and-paste mistake, since we just pulled bits [3:1] out of matched_rlar for attrindx. Applied to target-arm.next, thanks (and added a cc:stable tag). (I did wonder about v8M, but this whole block is not-M-profile; the register layout for RLAR and RBAR is the same, we just don't bother to fish out the SH and attr info since there's nowhere that M-profile needs to report it.) -- PMM
