Hi

On Fri, Sep 11, 2026 at 4:28 PM Marc-André Lureau
<[email protected]> wrote:
>
> Hi,
>
> HMP monitor supports printing $register expression. The lookup
> was done via GDB stub registers, and supplementary MonitorDef
> HMP-specific tables.
>
> Migrate HMP registers to use the GDB infrastructure and remove the
> legacy HMP MonitorDef. Use a "qemu-debug" register group, as they are
> aliases or synthetic registers, but gdb doesn't seem to care.
>
> Known behavioural changes on RISC-V: CSR lookup is now case-sensitive
> and vector registers now report "unkown register" instead of a
> target-specific message ("Unable to print the value of vector vreg 'v0'
> from this API")
>
> Signed-off-by: Marc-André Lureau <[email protected]>

ping? swap reviews?

> ---
> Marc-André Lureau (10):
>       hmp: don't crash on invalid register
>       gdbstub: fix next register base after register gaps
>       gdbstub: set feature->base_reg for dynamic features
>       target/i386: expose segment limits via GDB
>       monitor/hmp: add CPUClass::get_pc fallback for HMP $pc
>       target/m68k: expose system registers via GDB
>       target/sparc64: expose system registers via GDB
>       target/riscv: bypass smstateen check in debugger mode
>       target/riscv: expose register aliases via GDB
>       monitor/hmp: remove legacy MonitorDef infrastructure
>
>  configs/targets/i386-softmmu.mak          |   2 +-
>  configs/targets/m68k-softmmu.mak          |   2 +-
>  configs/targets/riscv32-linux-user.mak    |   2 +-
>  configs/targets/riscv32-softmmu.mak       |   2 +-
>  configs/targets/riscv64-bsd-user.mak      |   2 +-
>  configs/targets/riscv64-linux-user.mak    |   2 +-
>  configs/targets/riscv64-softmmu.mak       |   2 +-
>  configs/targets/sparc64-softmmu.mak       |   2 +-
>  configs/targets/x86_64-softmmu.mak        |   2 +-
>  gdbstub/gdb-xml/i386-segments.xml         |  14 +++
>  gdbstub/gdb-xml/m68k-system.xml           |  32 +++++++
>  gdbstub/gdb-xml/riscv-32bit-alias.xml     | 105 ++++++++++++++++++++++
>  gdbstub/gdb-xml/riscv-32bit-fpu-alias.xml |  40 +++++++++
>  gdbstub/gdb-xml/riscv-64bit-alias.xml     | 105 ++++++++++++++++++++++
>  gdbstub/gdb-xml/riscv-64bit-fpu-alias.xml |  46 ++++++++++
>  gdbstub/gdb-xml/sparc64-system.xml        |  22 +++++
>  gdbstub/gdbstub.c                         |  14 +--
>  include/hw/core/cpu.h                     |   2 +-
>  include/hw/core/sysemu-cpu-ops.h          |  16 ----
>  include/monitor/hmp.h                     |   6 --
>  include/qemu/typedefs.h                   |   1 -
>  monitor/hmp.c                             |  52 ++---------
>  target/arm/gdbstub.c                      |   8 +-
>  target/arm/gdbstub64.c                    |  10 ++-
>  target/i386/cpu.c                         |  32 -------
>  target/i386/gdbstub.c                     |  24 +++++
>  target/m68k/cpu.c                         |  22 -----
>  target/m68k/helper.c                      |  47 ++++++++++
>  target/ppc/gdbstub.c                      |   2 +-
>  target/riscv/cpu.c                        |   1 -
>  target/riscv/gdbstub.c                    |  52 ++++++++++-
>  target/riscv/internals.h                  |   3 -
>  target/riscv/monitor.c                    | 140 
> ------------------------------
>  target/riscv/tcg/csr.c                    |   3 +-
>  target/sparc/cpu.c                        |  19 ----
>  target/sparc/gdbstub.c                    |  38 ++++++++
>  target/xtensa/cpu.c                       |   2 +-
>  37 files changed, 562 insertions(+), 314 deletions(-)
> ---
> base-commit: 209b2afaface001c7d4d981e38f186afe7b24a50
> change-id: 20260910-query-reg-80cd59cf4707
>
> Best regards,
> --
> Marc-André Lureau <[email protected]>
>
>

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