On 4/9/26 17:57, Bin Meng wrote:
Implement the Config, WayEnable, and per-master WayMask registers
described by the PolarFire SoC MSS reference manual. Make WayEnable
monotonic and report the remaining register space as unimplemented.
Signed-off-by: Bin Meng <[email protected]>
Acked-by: Alistair Francis <[email protected]>
---
Changes in v2:
- Use the Resettable API instead of a legacy reset handler
MAINTAINERS | 2 +
include/hw/misc/mchp_pfsoc_l2cc.h | 30 +++++
hw/misc/mchp_pfsoc_l2cc.c | 180 ++++++++++++++++++++++++++++++
hw/misc/Kconfig | 3 +
hw/misc/meson.build | 1 +
5 files changed, 216 insertions(+)
create mode 100644 include/hw/misc/mchp_pfsoc_l2cc.h
create mode 100644 hw/misc/mchp_pfsoc_l2cc.c
diff --git a/include/hw/misc/mchp_pfsoc_l2cc.h
b/include/hw/misc/mchp_pfsoc_l2cc.h
new file mode 100644
index 0000000000..1b5b3888d5
--- /dev/null
+++ b/include/hw/misc/mchp_pfsoc_l2cc.h
@@ -0,0 +1,30 @@
+/*
+ * Microchip PolarFire SoC L2 cache controller
+ *
+ * Copyright (c) 2026 Process Mission
+ *
+ * Author:
+ * Bin Meng <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef MCHP_PFSOC_L2CC_H
+#define MCHP_PFSOC_L2CC_H
+
+#include "hw/core/register.h"
+#include "hw/core/sysbus.h"
+
+#define MCHP_PFSOC_L2CC_REG_SIZE 0x1000
+#define MCHP_PFSOC_L2CC_REG_NUM (MCHP_PFSOC_L2CC_REG_SIZE / 8)
+
+typedef struct MchpPfSoCL2ccState {
+ SysBusDevice parent;
Nitpicking, 'parent_obj'.
+ uint64_t regs[MCHP_PFSOC_L2CC_REG_NUM];
+ RegisterInfo regs_info[MCHP_PFSOC_L2CC_REG_NUM];
+} MchpPfSoCL2ccState;
