On 1/10/26 03:47, Alistair Francis wrote:
On Wed, 2026-09-30 at 19:45 +0200, Philippe Mathieu-Daudé wrote:
Use per-accelerator locals to make the differing conventions
explicit: TCG takes a MIP bitmask and value, KVM takes an IRQ
number and a level.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]>
Per
https://lore.kernel.org/qemu-devel/[email protected]/:
Reviewed-by: Daniel Henrique Barboza <[email protected]>
Reviewed-by: Alistair Francis <[email protected]>
Alistair
---
target/riscv/time_helper.c | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index ede1a4c2a34..29bbebb96fc 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -25,18 +25,24 @@
#include "system/kvm.h"
#include "system/tcg.h"
-static void riscv_accel_set_irq(RISCVCPU *cpu, int irq, int level)
+static void riscv_accel_set_irq(RISCVCPU *cpu,
+ int irq_or_mask, int level_or_value)
{
if (kvm_enabled()) {
+ int irq = irq_or_mask;
+ int level = level_or_value;
+
kvm_riscv_set_irq(cpu, irq, level);
}
if (tcg_enabled()) {
- riscv_cpu_update_mip(&cpu->env, irq, level);
+ uint64_t mask = irq_or_mask;
+ uint64_t value = level_or_value;
+
+ riscv_cpu_update_mip(&cpu->env, mask, value);
}
}
-
static void riscv_vstimer_cb(void *opaque)
{
RISCVCPU *cpu = opaque;
