On Wed, 2026-09-30 at 19:45 +0200, Philippe Mathieu-Daudé wrote: > RISCV-specific patches extracted from the bigger v3: > https://lore.kernel.org/qemu-devel/[email protected]/ > > - 1-3: document riscv_cpu_update_mip() and kvm_riscv_set_irq(), and > make the differing TCG (MIP mask) and KVM (IRQ number) argument > conventions of riscv_accel_set_irq() explicit > - 4: riscv_cpu_set_mode() calls riscv_cpu_interrupt() directly > - 5-6: add riscv_cpu_get_mip() and make it atomic > - 7: drop the zero-mask callers of riscv_cpu_update_mip() and assert > a non-zero mask
Applied patch 1-6 Applied to riscv-to-apply.next Alistair > > Patch 7 was drafted with AI assistance which suggested checking zero > mask was a no-op as not reachable so I added the AI-used-for trailer. > > Testing: CI pipeline > > Philippe Mathieu-Daudé (7): > target/riscv: Document riscv_cpu_update_mip() > target/riscv: Document kvm_riscv_set_irq() > target/riscv: Clarify riscv_accel_set_irq() arguments > target/riscv: Have riscv_cpu_set_mode() call riscv_cpu_interrupt() > target/riscv: Add riscv_cpu_get_mip() > target/riscv: Access MIP atomically > target/riscv: Skip redundant MIP updates > > target/riscv/cpu.h | 21 +++++++++++++++++++++ > target/riscv/kvm/kvm_riscv.h | 6 ++++++ > hw/intc/riscv_aclint.c | 2 +- > target/riscv/cpu.c | 9 ++++++++- > target/riscv/tcg/cpu_helper.c | 21 ++++++++++++++------- > target/riscv/tcg/csr.c | 6 ++++-- > target/riscv/time_helper.c | 21 ++++++++++++++++++--- > 7 files changed, 72 insertions(+), 14 deletions(-)
