On Wed, Sep 30, 2026 at 5:31 PM Conor Dooley <[email protected]> wrote: > > On Fri, Sep 04, 2026 at 11:57:36PM +0800, Bin Meng wrote: > > The 64-bit cached and non-cached windows alias the complete physical > > DDR from offset zero. Treating them as only the portion above 1 GiB > > This is not strictly true, how these regions overlap depends on how the > FPGA itself is configured. In the past, the regions were set up > sequentially and someone may choose to set their device up that way if > they want to, provided they change their devicetree to match. > > I think the change is worth making, but the commit doing so should cite > reality and explain that this aliasing is the case in the reference > designs provided by microchip, not present it as the whole truth. > > Ditto for the comment.
Will update the commit message and comment in v3. > > > leaves valid Icicle Kit memory nodes unbacked with the board's 2 GiB. > > > > Map both high windows over the full machine RAM. > > > > Signed-off-by: Bin Meng <[email protected]> > > Reviewed-by: Chao Liu <[email protected]> > > --- > > > > (no changes since v1) > > > > hw/riscv/microchip_pfsoc.c | 18 +++++++++++++++--- > > 1 file changed, 15 insertions(+), 3 deletions(-) > > Regards, Bin
