The e5500 and e6500 implement cmpb, prtyw and prtyd, as listed in table 3-7 of their reference manuals.
Enable only the byte comparison and parity feature flags on these cores. The e500mc explicitly excludes cmpb and prtyw in table 3-1, so keep these features disabled there. Unsupported floating-point instructions and extended FPSCR access remain disabled. Reference: - E500MCRM (Rev.3), section 3.1.1 https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf - E5500RM (Rev.4), section 3.1.1 and 3.4.3.1.3 https://www.nxp.com/webapp/Download?colCode=E5500RM - E6500RM (Rev.0), section 3.1.1 and 3.4.3.1.3 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu_init.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index f2a342b076..1c02354e11 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -3216,7 +3216,7 @@ POWERPC_FAMILY(e5500)(ObjectClass *oc, const void *data) PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | PPC_64B | PPC_POPCNTB | PPC_POPCNTWD; pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | - PPC2_FP_CVT_S64; + PPC2_FP_CVT_S64 | PPC2_CMPB_ISA205 | PPC2_PRTY_ISA205; pcc->msr_mask = (1ull << MSR_CM) | (1ull << MSR_GS) | (1ull << MSR_UCLE) | @@ -3265,7 +3265,8 @@ POWERPC_FAMILY(e6500)(ObjectClass *oc, const void *data) PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC | PPC_64B | PPC_POPCNTB | PPC_POPCNTWD | PPC_ALTIVEC; pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206 | - PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206; + PPC2_FP_CVT_S64 | PPC2_ATOMIC_ISA206 | + PPC2_CMPB_ISA205 | PPC2_PRTY_ISA205; pcc->msr_mask = (1ull << MSR_CM) | (1ull << MSR_GS) | (1ull << MSR_UCLE) | -- 2.53.0
