U-Boot programs the L1 data cache stash identifier before entering its C initialization code. The e500mc, e5500 and e6500 core manuals define L1CSR2 as a 32-bit SPR with number 606 (0x25e) and reset value zero.
Expose the register on all three cores, excluding e500v1 and e500v2. Reference: - E500MCRM (Rev.3), section 2.14.3 https://www.nxp.com/docs/en/reference-manual/E500MCRM.pdf - E5500RM (Rev.4), section 2.14.3 https://www.nxp.com/webapp/Download?colCode=E5500RM - E6500RM (Rev.0), section 2.11.3 https://www.nxp.com/docs/en/reference-manual/E6500RM.pdf Signed-off-by: Bin Meng <[email protected]> --- target/ppc/cpu.h | 1 + target/ppc/cpu_init.c | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index abcbcf3c18..d3f1c82730 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2038,6 +2038,7 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_BOOKE_DSRR1 (0x23F) #define SPR_BOOKE_SPRG8 (0x25C) #define SPR_BOOKE_SPRG9 (0x25D) +#define SPR_Exxx_L1CSR2 (0x25E) #define SPR_BOOKE_MAS0 (0x270) #define SPR_BOOKE_MAS1 (0x271) #define SPR_BOOKE_MAS2 (0x272) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 23f25a56c0..e5856b5b1d 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2965,6 +2965,10 @@ static void init_proc_e500(CPUPPCState *env, int version) &spr_read_generic, &spr_write_e500_l1csr1, 0x00000000); if (version != fsl_e500v1 && version != fsl_e500v2) { + spr_register(env, SPR_Exxx_L1CSR2, "L1CSR2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_read_generic, &spr_write_generic32, + 0x00000000); spr_register(env, SPR_Exxx_L2CSR0, "L2CSR0", SPR_NOACCESS, SPR_NOACCESS, &spr_read_generic, &spr_write_e500_l2csr0, -- 2.53.0
