This patch implements the following instructions that are part of
the Dense Math Facility in RFC 02653 Power ISA 3.2 :
DMXX{MF, MT}ACC and DMSETACCZ
These instructions have the exact same opcodes as the older equivalent
vector instructions. This is handled using overlapping pattern groups.
Signed-off-by: Chinmay Rath <[email protected]>
---
target/ppc/insn32.decode | 20 +++++++----
target/ppc/translate/dmf-impl.c.inc | 55 +++++++++++++++++++++++++++++
2 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 1d3ab1e046..f718d550dc 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -1429,12 +1429,6 @@ XVTLSBB 111100 ... -- 00010 ..... 111011011 . -
@XX2_bf_xb
@XL_s ......-------------- s:1 .......... - &XL_s
RFEBB 010011-------------- . 0010010010 - @XL_s
-## Accumulator Instructions
-
-XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
-XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
-XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
-
## VSX Vector Logical instructions
XXLAND 111100 ..... ..... ..... 10000010 ... @XX3
@@ -1547,6 +1541,20 @@ VMODUQ 000100 ..... ..... ..... 11000001011
@VX
## DMF Instructions
+## DMF accumulator instructions overlap with the existing accumulator ones.
+{
+ DMXXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
+ XXMFACC 011111 ... -- 00000 ----- 0010110001 - @X_a
+}
+{
+ DMXXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
+ XXMTACC 011111 ... -- 00001 ----- 0010110001 - @X_a
+}
+{
+ DMSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
+ XXSETACCZ 011111 ... -- 00011 ----- 0010110001 - @X_a
+}
+
DMSETDMRZ 011111 ... -- 00010 ----- 0010110001 - @X_a
DMXXEXTFDMR512 111100 ... -- .... . .... - 11100010 ..- @XX3_abp_as_p
diff --git a/target/ppc/translate/dmf-impl.c.inc
b/target/ppc/translate/dmf-impl.c.inc
index 4afa269f12..45aabe2a4d 100644
--- a/target/ppc/translate/dmf-impl.c.inc
+++ b/target/ppc/translate/dmf-impl.c.inc
@@ -105,3 +105,58 @@ static bool trans_DMXOR(DisasContext *ctx, arg_DMXOR *a)
}
return true;
}
+
+static bool trans_DMXXMFACC(DisasContext *ctx, arg_DMXXMFACC *a)
+{
+ TCGv_i128 temp;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA320);
+ REQUIRE_DM(ctx);
+ REQUIRE_VSX(ctx);
+
+ temp = tcg_temp_new_i128();
+ for (int i = 0; i < 4; i++) {
+ get_dmr_row(temp, a->ra, i);
+ set_vsr_full((4 * a->ra) + i, temp);
+ }
+ return true;
+}
+
+static bool trans_DMXXMTACC(DisasContext *ctx, arg_DMXXMTACC *a)
+{
+ TCGv_i128 temp;
+ TCGv_i64 hi, lo;
+
+ REQUIRE_INSNS_FLAGS2(ctx, ISA320);
+ REQUIRE_DM(ctx);
+ REQUIRE_VSX(ctx);
+
+ temp = tcg_temp_new_i128();
+ for (int i = 0; i < 4; i++) {
+ get_vsr_full(temp, (4 * a->ra) + i);
+ set_dmr_row(a->ra, i, temp);
+ }
+
+ /*
+ * As per ISA 3.2, the last four rows of the DMR corresponding
+ * to the target ACC are set to zero.
+ */
+ hi = tcg_constant_i64(0);
+ lo = tcg_constant_i64(0);
+ tcg_gen_concat_i64_i128(temp, lo, hi);
+ for (int i = 4; i < 8; i++) {
+ set_dmr_row(a->ra, i, temp);
+ }
+ return true;
+}
+
+static bool trans_DMSETACCZ(DisasContext *ctx, arg_DMSETACCZ *a)
+{
+ /*
+ * As per ISA 3.2, the last four rows of the DMR corresponding
+ * to the target ACC are set to zero.
+ * So essentially, all rows are set to zero.
+ * This makes this instruction equivalent to DMSETDMRZ.
+ */
+ return trans_DMSETDMRZ(ctx, a);
+}
--
2.55.0
