This patch implements DMMR and DMXOR instructions, that are part of the
Dense Math Facility in RFC 02653, Power ISA 3.2

Signed-off-by: Chinmay Rath <[email protected]>
---
 target/ppc/insn32.decode            |  6 ++++++
 target/ppc/translate/dmf-impl.c.inc | 27 +++++++++++++++++++++++++++
 2 files changed, 33 insertions(+)

diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 2a9733d6fd..1d3ab1e046 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -231,6 +231,9 @@
 &X_a            ra
 @X_a            ...... ra:3 .. ..... ..... .......... .         &X_a
 
+&X_ab           ra rb
+@X_ab           ...... ra:3 .. ..... rb:3 .. ...........        &X_ab
+
 &X_tl           rt l
 @X_tl           ...... rt:5 ... l:2 ..... .......... .          &X_tl
 
@@ -1552,6 +1555,9 @@ DMXXINSTDMR512  111100 ... -- .... . .... - 11101010 ..-  
  @XX3_abp_as_p
 DMXXEXTFDMR256  111100 ... ------ . .... . 111100100 .-     @XX2_bp_as_p
 DMXXINSTDMR256  111100 ... ------ . .... . 111100101 .-     @XX2_bp_as_p
 
+DMMR            011111 ... -- 00110 ... -- 0010110001 -     @X_ab
+DMXOR           011111 ... -- 00111 ... -- 0010110001 -     @X_ab
+
 ## SLB Management Instructions
 
 SLBIE           011111 ----- ----- ..... 0110110010 -   @X_rb
diff --git a/target/ppc/translate/dmf-impl.c.inc 
b/target/ppc/translate/dmf-impl.c.inc
index 5409ba8836..4afa269f12 100644
--- a/target/ppc/translate/dmf-impl.c.inc
+++ b/target/ppc/translate/dmf-impl.c.inc
@@ -78,3 +78,30 @@ TRANS_FLAGS2(ISA320, DMXXEXTFDMR512, do_ext_inst_512, true)
 TRANS_FLAGS2(ISA320, DMXXINSTDMR512, do_ext_inst_512, false)
 TRANS_FLAGS2(ISA320, DMXXEXTFDMR256, do_ext_inst_256, true)
 TRANS_FLAGS2(ISA320, DMXXINSTDMR256, do_ext_inst_256, false)
+
+static bool trans_DMMR(DisasContext *ctx, arg_DMMR *a)
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA320);
+    REQUIRE_DM(ctx);
+
+    TCGv_i128 temp;
+    temp = tcg_temp_new_i128();
+    for (int row = 0; row < 8; row++) {
+        get_dmr_row(temp, a->rb, row);
+        set_dmr_row(a->ra, row, temp);
+    }
+    return true;
+}
+
+static bool trans_DMXOR(DisasContext *ctx, arg_DMXOR *a)
+{
+    REQUIRE_INSNS_FLAGS2(ctx, ISA320);
+    REQUIRE_DM(ctx);
+
+    for (int row = 0; row < 8; row++) {
+        tcg_gen_gvec_xor(MO_64, dmr_row_offset(a->ra, row),
+                         dmr_row_offset(a->ra, row), dmr_row_offset(a->rb, 
row),
+                         16, 16);
+    }
+    return true;
+}
-- 
2.55.0


Reply via email to