For now, we keep the global common_* symbols defined.
Signed-off-by: Pierrick Bouvier <[email protected]>
---
target/hexagon/common-semi-target.c | 63 ++++++++++++++++++++++++-----
target/hexagon/cpu.c | 2 +
target/hexagon/internal.h | 2 +
3 files changed, 58 insertions(+), 9 deletions(-)
diff --git a/target/hexagon/common-semi-target.c
b/target/hexagon/common-semi-target.c
index 210d33e54e2..b97ed6796f8 100644
--- a/target/hexagon/common-semi-target.c
+++ b/target/hexagon/common-semi-target.c
@@ -8,44 +8,89 @@
#include "qemu/osdep.h"
#include "cpu.h"
-#include "cpu_helper.h"
#include "semihosting/common-semi.h"
+#include "internal.h"
-uint64_t common_semi_arg(CPUState *cs, int argno)
+static uint64_t hexagon_semi_arg(CPUState *cs, int argno)
{
CPUHexagonState *env = cpu_env(cs);
return env->gpr[HEX_REG_R00 + argno];
}
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
+static void hexagon_semi_set_ret(CPUState *cs, uint64_t ret)
{
CPUHexagonState *env = cpu_env(cs);
env->gpr[HEX_REG_R00] = ret;
}
-void common_semi_set_err(CPUState *cs, int err)
+static void hexagon_semi_set_err(CPUState *cs, int err)
{
CPUHexagonState *env = cpu_env(cs);
env->gpr[HEX_REG_R01] = err;
}
-bool common_semi_sys_exit_is_extended(CPUState *cs)
+static bool hexagon_semi_is_64bit(CPUState *cs)
{
return false;
}
+static bool hexagon_semi_sys_exit_is_extended(CPUState *cs)
+{
+ return false;
+}
+
+static uint64_t hexagon_semi_stack_bottom(CPUState *cs)
+{
+ CPUHexagonState *env = cpu_env(cs);
+ return env->gpr[HEX_REG_SP];
+}
+
+static bool hexagon_semi_has_synccache(CPUState *cs)
+{
+ return false;
+}
+
+const SemihostingCPUOps hexagon_semihosting_ops = {
+ .arg = hexagon_semi_arg,
+ .set_ret = hexagon_semi_set_ret,
+ .set_err = hexagon_semi_set_err,
+ .is_64bit = hexagon_semi_is_64bit,
+ .sys_exit_is_extended = hexagon_semi_sys_exit_is_extended,
+ .stack_bottom = hexagon_semi_stack_bottom,
+ .has_synccache = hexagon_semi_has_synccache,
+};
+
+uint64_t common_semi_arg(CPUState *cs, int argno)
+{
+ return hexagon_semi_arg(cs, argno);
+}
+
+void common_semi_set_ret(CPUState *cs, uint64_t ret)
+{
+ hexagon_semi_set_ret(cs, ret);
+}
+
+void common_semi_set_err(CPUState *cs, int err)
+{
+ hexagon_semi_set_err(cs, err);
+}
+
bool is_64bit_semihosting(CPUArchState *env)
{
- return false;
+ return hexagon_semi_is_64bit(env_cpu(env));
+}
+
+bool common_semi_sys_exit_is_extended(CPUState *cs)
+{
+ return hexagon_semi_sys_exit_is_extended(cs);
}
uint64_t common_semi_stack_bottom(CPUState *cs)
{
- CPUHexagonState *env = cpu_env(cs);
- return env->gpr[HEX_REG_SP];
+ return hexagon_semi_stack_bottom(cs);
}
bool common_semi_has_synccache(CPUArchState *env)
{
- return false;
+ return hexagon_semi_has_synccache(env_cpu(env));
}
diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c
index 1f7d8a8df70..24e39531b95 100644
--- a/target/hexagon/cpu.c
+++ b/target/hexagon/cpu.c
@@ -837,6 +837,8 @@ static void hexagon_cpu_class_init(ObjectClass *c, const
void *data)
#ifndef CONFIG_USER_ONLY
cc->sysemu_ops = &hexagon_sysemu_ops;
dc->vmsd = &vmstate_hexagon_cpu;
+ /* semihosting is only supported in system mode for Hexagon */
+ cc->semi_ops = &hexagon_semihosting_ops;
#endif
#ifdef CONFIG_TCG
cc->tcg_ops = &hexagon_tcg_ops;
diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h
index 05d1129916e..38eb84f319d 100644
--- a/target/hexagon/internal.h
+++ b/target/hexagon/internal.h
@@ -30,6 +30,8 @@ void hexagon_debug_qreg(CPUHexagonState *env, int regnum);
void hexagon_debug(CPUHexagonState *env);
void hexagon_dump(CPUHexagonState *env, FILE *f, int flags);
+extern const struct SemihostingCPUOps hexagon_semihosting_ops;
+
extern const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS];
#ifndef CONFIG_USER_ONLY
extern const char * const hexagon_sregnames[];
--
2.43.0
