For now, we keep the global common_* symbols defined.
Signed-off-by: Pierrick Bouvier <[email protected]>
---
target/riscv/common-semi-target.c | 62 +++++++++++++++++++++++++++----
target/riscv/cpu.c | 4 ++
target/riscv/internals.h | 2 +
3 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/target/riscv/common-semi-target.c
b/target/riscv/common-semi-target.c
index 38a00e160c3..7fa3bef6883 100644
--- a/target/riscv/common-semi-target.c
+++ b/target/riscv/common-semi-target.c
@@ -11,43 +11,89 @@
#include "qemu/osdep.h"
#include "cpu.h"
#include "semihosting/common-semi.h"
+#include "internals.h"
-uint64_t common_semi_arg(CPUState *cs, int argno)
+static uint64_t riscv_semi_arg(CPUState *cs, int argno)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
return env->gpr[xA0 + argno];
}
-void common_semi_set_ret(CPUState *cs, uint64_t ret)
+static void riscv_semi_set_ret(CPUState *cs, uint64_t ret)
{
RISCVCPU *cpu = RISCV_CPU(cs);
CPURISCVState *env = &cpu->env;
env->gpr[xA0] = ret;
}
+static void riscv_semi_set_err(CPUState *cs, int err)
+{
+}
+
+static bool riscv_semi_is_64bit(CPUState *cs)
+{
+ return riscv_cpu_mxl(cpu_env(cs)) != MXL_RV32;
+}
+
+static bool riscv_semi_sys_exit_is_extended(CPUState *cs)
+{
+ return riscv_semi_is_64bit(cs);
+}
+
+static uint64_t riscv_semi_stack_bottom(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ return env->gpr[xSP];
+}
+
+static bool riscv_semi_has_synccache(CPUState *cs)
+{
+ return true;
+}
+
+const SemihostingCPUOps riscv_semihosting_ops = {
+ .arg = riscv_semi_arg,
+ .set_ret = riscv_semi_set_ret,
+ .set_err = riscv_semi_set_err,
+ .is_64bit = riscv_semi_is_64bit,
+ .sys_exit_is_extended = riscv_semi_sys_exit_is_extended,
+ .stack_bottom = riscv_semi_stack_bottom,
+ .has_synccache = riscv_semi_has_synccache,
+};
+
+uint64_t common_semi_arg(CPUState *cs, int argno)
+{
+ return riscv_semi_arg(cs, argno);
+}
+
+void common_semi_set_ret(CPUState *cs, uint64_t ret)
+{
+ riscv_semi_set_ret(cs, ret);
+}
+
void common_semi_set_err(CPUState *cs, int err)
{
+ riscv_semi_set_err(cs, err);
}
bool is_64bit_semihosting(CPUArchState *env)
{
- return riscv_cpu_mxl(env) != MXL_RV32;
+ return riscv_semi_is_64bit(env_cpu(env));
}
bool common_semi_sys_exit_is_extended(CPUState *cs)
{
- return is_64bit_semihosting(cpu_env(cs));
+ return riscv_semi_sys_exit_is_extended(cs);
}
uint64_t common_semi_stack_bottom(CPUState *cs)
{
- RISCVCPU *cpu = RISCV_CPU(cs);
- CPURISCVState *env = &cpu->env;
- return env->gpr[xSP];
+ return riscv_semi_stack_bottom(cs);
}
bool common_semi_has_synccache(CPUArchState *env)
{
- return true;
+ return riscv_semi_has_synccache(env_cpu(env));
}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index da4c1a090b9..63c709ac738 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3053,6 +3053,10 @@ static void riscv_cpu_common_class_init(ObjectClass *c,
const void *data)
cc->gdb_arch_name = riscv_gdb_arch_name;
#ifdef CONFIG_TCG
cc->tcg_ops = &riscv_tcg_ops;
+#if !defined(CONFIG_USER_ONLY) || defined(CONFIG_LINUX)
+ /* semihosting is not supported for bsd-user */
+ cc->semi_ops = &riscv_semihosting_ops;
+#endif
#endif /* CONFIG_TCG */
device_class_set_props(dc, riscv_cpu_properties);
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index 5d84e4de960..f17d011d22f 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -206,6 +206,8 @@ static inline target_ulong get_xepc_mask(CPURISCVState *env)
bool riscv_cpu_has_work(CPUState *cs);
#endif
+extern const struct SemihostingCPUOps riscv_semihosting_ops;
+
/* Zjpm addr masking routine */
static inline target_ulong adjust_addr_body(CPURISCVState *env,
target_ulong addr,
--
2.43.0
