From: Shaju Abraham <[email protected]> Include cpu-idregs.h.inc multiple times with different definitions for the X-macros. This will generate tables for all Arm64 ID registers and their fields. Additionally, initialize the tables with all architecturally defined values. These tables will be consumed by the property layer in future patches.
Co-authored-by: Khushit Shah <[email protected]> Signed-off-by: Khushit Shah <[email protected]> Signed-off-by: Shaju Abraham <[email protected]> Signed-off-by: Eric Auger <[email protected]> --- v9 -> v10 - fix tabs - initialize writable_mask - Use ValueRange instead of Value v7 -> v8 Adaptation after removal of struct ArmIdRegArchVal v5 -> v6 - restored support of enum values --- target/arm/cpu-idregs.c | 93 +++++++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 1 + 2 files changed, 94 insertions(+) create mode 100644 target/arm/cpu-idregs.c diff --git a/target/arm/cpu-idregs.c b/target/arm/cpu-idregs.c new file mode 100644 index 0000000000..122ef9c82d --- /dev/null +++ b/target/arm/cpu-idregs.c @@ -0,0 +1,93 @@ +/* + * ARM ID register field table. + * + * Builds the per-id-register field descriptor arrays and the global + * arm_idregs[] table. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qapi/error.h" +#include "cpu.h" +#include "cpu-idregs.h" + +/* + * Generate an array of architecturally defined value ranges for each field + * that has enum / ValueRange constraints. + */ + +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) { .lo = (_lo), .hi = (_hi) } + +#define IDREG_START(reg) +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_ENUM(reg, field, shift, length, ...) \ + static const ARM64SysRegArchValueRange reg##_##field##_arch_value_ranges[] = { \ + __VA_ARGS__ \ + }; + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_ENUM +#undef IDREG_ARCH_VALUE_RANGE + +/* generate an array of per-register ArmIdRegField[] descriptors */ + +#define IDREG_START(reg) \ + static ARM64SysRegField reg##_fields[] = { + +#define IDREG_END(reg) \ + }; + +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) + +#define IDREG_FIELD_ENUM(reg, field, _shift, _length, ...) \ + { \ + .name = #field, \ + .index = reg##_IDX, \ + .shift = (_shift), \ + .length = (_length), \ + .arch_value_ranges = reg##_##field##_arch_value_ranges, \ + .arch_value_ranges_count = \ + ARRAY_SIZE(reg##_##field##_arch_value_ranges), \ + }, + +#define IDREG_FIELD(reg, field, _shift, _length) \ + { \ + .name = #field, \ + .index = reg##_IDX, \ + .shift = (_shift), \ + .length = (_length), \ + }, + +#include "cpu-idregs.h.inc" + +#undef IDREG_START +#undef IDREG_END +#undef IDREG_FIELD +#undef IDREG_FIELD_ENUM +#undef IDREG_ARCH_VALUE_RANGE + +/* generate an array of top level ID registers */ + +#define IDREG_END(reg) +#define IDREG_FIELD(reg, field, shift, length) +#define IDREG_FIELD_ENUM(reg, field, shift, length, ...) +#define IDREG_ARCH_VALUE_RANGE(_lo, _hi) + +#define IDREG_START(reg) \ + [reg##_IDX] = { \ + .name = #reg, \ + .index = reg##_IDX, \ + .fields = reg##_fields, \ + .fields_count = ARRAY_SIZE(reg##_fields), \ + .writable_mask = 0ULL, \ + }, + +ARM64SysReg arm64_id_regs[NUM_ID_IDX] = { +#include "cpu-idregs.h.inc" +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index 0369f96b4c..384d90c530 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -30,6 +30,7 @@ arm_common_user_system_ss.add(when: 'TARGET_AARCH64', if_true: files( arm_common_system_ss.add(files( 'arm-qmp-cmds.c', + 'cpu-idregs.c', )) arm_system_ss.add(when: 'CONFIG_KVM', if_true: files('hyp_gdbstub.c', 'kvm.c')) arm_system_ss.add(when: 'CONFIG_HVF', if_true: files('hyp_gdbstub.c')) -- 2.53.0
